SY100EPT28L Datasheet: 3.3V LVTTL-to-Differential LVPECL and Differential LVPECL-to-LVTTL Translator





SY100EPT28L 3.3V LVTTL-to-Differential LVPECL and Differential LVPECL-to-LVTTL Translator Datasheet

Part Number SY100EPT28L
Description 3.3V LVTTL-to-Differential LVPECL and Differential LVPECL-to-LVTTL Translator
Manufacture Microchip
Total Page 14 Pages
PDF Download Download SY100EPT28L Datasheet PDF

Features: SY100EPT28L 3.3V LVTTL-to-Differential L VPECL and Differential LVPECL-to-LVTTL Translator Features • 3.3V ±10% Pow er Supply • Guaranteed AC Parameters over Temperature: fMAX > 275 MHz (LVTTL ) • <2.5 ns LVPECL-to-LVTTL Propagati on Delay • <600 ps LVTTL-to-LVPECL Pr opagation Delay • Industrial Temperat ure Range: –40°C to +85°C • Avail able in 8-Lead MSOP and SOIC packages General Description The SY100EPT28L is a differential LVPECL-to-LVTTL translat or and an LVTTL-to-differential LVPECL translator in a single package. Because LVPECL (Positive ECL) levels are used, only +3.3V and ground are required. Th e small outline 8-pin package and the d ual translation design of the EPT28L ma kes it ideal for applications that are sending and receiving signals across a backplane. Under open input conditions, the /D_LVPECL input will be biased at VCC/2 and the D_LVPECL input will be pu lled to GND. This condition will force the Q_LVTTL to a low, ensuring stability. The 100k series includes temperature c.

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SY100EPT28L
3.3V LVTTL-to-Differential LVPECL and
Differential LVPECL-to-LVTTL Translator
Features
• 3.3V ±10% Power Supply
• Guaranteed AC Parameters over Temperature:
fMAX > 275 MHz (LVTTL)
• <2.5 ns LVPECL-to-LVTTL Propagation Delay
• <600 ps LVTTL-to-LVPECL Propagation Delay
• Industrial Temperature Range: –40°C to +85°C
• Available in 8-Lead MSOP and SOIC packages
General Description
The SY100EPT28L is a differential LVPECL-to-LVTTL
translator and an LVTTL-to-differential LVPECL
translator in a single package. Because LVPECL
(Positive ECL) levels are used, only +3.3V and ground
are required. The small outline 8-pin package and the
dual translation design of the EPT28L makes it ideal for
applications that are sending and receiving signals
across a backplane.
Under open input conditions, the /D_LVPECL input will
be biased at VCC/2 and the D_LVPECL input will be
pulled to GND. This condition will force the Q_LVTTL to
a low, ensuring stability.
The 100k series includes temperature compensation.
Thus, logic levels are constant over temperature.
Package Types
SY100EPT28L
8-Lead MSOP (K)
8-Lead SOIC (Z)
(Top View)
D_LVPECL 1
/D_LVPECL 2
LVPECL
Q_LVPECL 3
/Q_LVPECL 4
8 VCC
7 Q_LVTTL
LVTTL
6 D_LVTTL
5 GND
2018 Microchip Technology Inc.
DS20006067A-page 1

                    
                    






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