SN54CDC341 Datasheet | 1-LINE TO 8-LINE CLOCK DRIVER





(Datasheet) SN54CDC341 Datasheet PDF Download

Part Number SN54CDC341
Description 1-LINE TO 8-LINE CLOCK DRIVER
Manufacture etcTI
Total Page 10 Pages
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Features: SN54CDC341 1-LINE TO 8-LINE CLOCK DRIVER D Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generatio n Applications D TTL-Compatible Inputs and Outputs D Distributes One Clock Inp ut to Eight Outputs D Distributed VCC a nd Ground Pins Reduce Switching Noise D High-Drive Outputs (– 48-mA IOH, 48- mA IOL) D State-of-the-Art EPIC-ΙΙB℠¢ BiCMOS Design Significantly Reduces P ower Dissipation D Package Options Incl ude Ceramic Flatpacks (W), Ceramic Chip Carriers (FK), and Ceramic (J) 300-mil DIPS SGAS005A – MARCH 1996 – REVI SED JULY 1997 J OR W PACKAGE (TOP VIEW) VCC 1G 2G A P0 P1 VCC 2Y4 2Y3 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 1Y1 18 1Y 2 17 GND 16 1Y3 15 1Y4 14 GND 13 2Y1 12 2Y2 11 GND FK PACKAGE (TOP VIEW) 2G 1G VCC VCC 1Y1 description The SN54CD C341 is a high-performance clockdriver circuit that distributes one (A) input signal to eight (Y) outputs with minimu m skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a l.

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SN54CDC341
1-LINE TO 8-LINE CLOCK DRIVER
D Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D TTL-Compatible Inputs and Outputs
D Distributes One Clock Input to Eight
Outputs
D Distributed VCC and Ground Pins Reduce
Switching Noise
D High-Drive Outputs (– 48-mA IOH,
48-mA IOL)
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Package Options Include Ceramic
Flatpacks (W), Ceramic Chip Carriers (FK),
and Ceramic (J) 300-mil DIPS
SGAS005A – MARCH 1996 – REVISED JULY 1997
J OR W PACKAGE
(TOP VIEW)
VCC
1G
2G
A
P0
P1
VCC
2Y4
2Y3
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 1Y1
18 1Y2
17 GND
16 1Y3
15 1Y4
14 GND
13 2Y1
12 2Y2
11 GND
FK PACKAGE
(TOP VIEW)
description
The SN54CDC341 is a high-performance clock-
driver circuit that distributes one (A) input signal to
eight (Y) outputs with minimum skew for clock
distribution. Through the use of the control pins
(1G and 2G), the outputs can be placed in a low
state regardless of the A input.
The propagation delays are adjusted at the factory
using the P0 and P1 pins. These pins are not
intended for customer use and should be strapped
to GND.
A
P0
P1
VCC
2Y4
4
5
6
7
8
3 2 1 20 19
18 1Y2
17 GND
16 1Y3
15 1Y4
14 GND
9 10 11 12 13
The SN54CDC341 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE
INPUTS
OUTPUTS
1G 2G
A 1Y1 – 1Y4 2Y1 – 2Y4
XXL
L
L
L LH
L
L
L HH
L
H
HLH
H
L
HHH
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
•POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1

                    
        






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