SN74SSTV32867-EP

www.ti.com SN74SSTV32867-EP 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS SCES664 – SEPTEMBER 2006 FEATURES Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 85°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree (1) Member of the Texas Instruments Widebus+™ Family (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated DIMM Load Supports SSTL_2 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the RESET Input RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 26-bit registered buffer is designe...