74VHC02 Datasheet: Quad 2-Input NOR Gate





74VHC02 Quad 2-Input NOR Gate Datasheet

Part Number 74VHC02
Description Quad 2-Input NOR Gate
Manufacture ON Semiconductor
Total Page 6 Pages
PDF Download Download 74VHC02 Datasheet PDF

Features: 74VHC02 — Quad 2-Input NOR Gate 74VHC 02 Quad 2-Input NOR Gate Features ■ H igh Speed: tPD = 3.6ns (Typ.) at VCC = 5V ■ Low power dissipation: ICC = 2µ A (Max.) at TA = 25°C ■ High noise i mmunity: VNIH = VNIL = 28% VCC (Min.) Power down protection is provided on all inputs ■ Low noise: VOLP = 0.8V (Max.) ■ Pin and function compatible with 74HC02 General Description The VH C02 is an advanced high-speed CMOS 2-In put NOR Gate fabricated with silicon ga te CMOS technology. It achieves the hig h-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The in ternal circuit is composed of 3 stages, including buffer output, which provide high noise immunity and stable output. An input protection circuit insures th at 0V to 7V can be applied to the input pins without regard to the supply volt age. This device can be used to interfa ce 5V to 3V systems and two supply syst ems such as battery backup. This circuit prevents device destruction due to mis.

Keywords: 74VHC02, datasheet, pdf, ON Semiconductor, Quad, 2-Input, NOR, Gate, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

74VHC02
Quad 2-Input NOR Gate
Features
High Speed: tPD = 3.6ns (Typ.) at VCC = 5V
Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (Min.)
Power down protection is provided on all inputs
Low noise: VOLP = 0.8V (Max.)
Pin and function compatible with 74HC02
General Description
The VHC02 is an advanced high-speed CMOS 2-Input
NOR Gate fabricated with silicon gate CMOS technol-
ogy. It achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The internal circuit is
composed of 3 stages, including buffer output, which
provide high noise immunity and stable output. An input
protection circuit insures that 0V to 7V can be applied to
the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and
two supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply
and input voltages.
Ordering Information
Order Number
Package
Number
Package Description
74VHC02M
74VHC02SJ
74VHC02MTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1992 Semiconductor Components Industries, LLC.
August-2017, Rev. 2
Publication Order Number:
74VHC02/D

                 






Index : 0  1  2  3   4  5  6  7   8  9  A  B   C  D  E  F   G  H  I  J   K  L  M  N   O  P  Q  R   S  T  U  V   W  X  Y  Z
@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)