MPC9352 Datasheet: 3.3V/2.5V 1:11 LVCMOS Zero Delay Clock Generator





MPC9352 3.3V/2.5V 1:11 LVCMOS Zero Delay Clock Generator Datasheet

Part Number MPC9352
Description 3.3V/2.5V 1:11 LVCMOS Zero Delay Clock Generator
Manufacture IDT
Total Page 16 Pages
PDF Download Download MPC9352 Datasheet PDF

Features: 3.3V/2.5V 1:11 LVCMOS Zero Delay Clock G enerator PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2 016 MPC9352 DATASHEET The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL b ased clock generator targeted for high performance clock tree applications. Wi th output frequencies up to 200 MHz and output skews lower than 200 ps, the de vice meets the needs of most demanding clock applications. Features • Config urable 11 Outputs LVCMOS PLL Clock Gene rator • Fully Integrated PLL • Wide Range of Output Clock Frequency of 16. 67 MHz to 200 MHz • Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3  2, 2  3, 1  3 and 1  2 • 2.5 V and 3.3 V LVCMOS Com patible • Maximum Output Skew of 200 ps • Supports Zero-Delay Applications • Designed for High-Performance Tele com, Networking and Computing Applicati ons • 32-Lead LQFP Package, Pb-Free Ambient Temperature Range –40°C t o +85°C • For functional replacement use 8T49N285 MPC9352 LOW VOLTAGE 3.3 V/2.5 V LVCMOS 1:11.

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3.3V/2.5V 1:11 LVCMOS Zero Delay
Clock Generator
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016
MPC9352
DATASHEET
The MPC9352 is a 3.3 V or 2.5 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 200 MHz and output skews lower than 200 ps, the device meets the needs of
most demanding clock applications.
Features
• Configurable 11 Outputs LVCMOS PLL Clock Generator
• Fully Integrated PLL
• Wide Range of Output Clock Frequency of 16.67 MHz to 200 MHz
• Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3 2, 2 3,
1 3 and 1 2
• 2.5 V and 3.3 V LVCMOS Compatible
• Maximum Output Skew of 200 ps
• Supports Zero-Delay Applications
• Designed for High-Performance Telecom, Networking and Computing
Applications
• 32-Lead LQFP Package, Pb-Free
• Ambient Temperature Range –40°C to +85°C
For functional replacement use 8T49N285
MPC9352
LOW VOLTAGE
3.3 V/2.5 V LVCMOS 1:11
CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
The MPC9352 is a fully 3.3 V or 2.5 V compatible PLL clock generator and clock driver. The device has the capability to gen-
erate output clock signals of 16.67 to 200 MHz from external clock sources. The internal PLL is optimized for its frequency range
and does not require external lock filter components. One output of the MPC9352 has to be connected to the PLL feedback input
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-
cation factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different, but phase-aligned, clock frequencies.
The PLL of the MPC9352 minimizes the propagation delay, and therefore, supports zero-delay applications. All inputs and out-
puts are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50transmission lines. Alternatively, each
output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC9352 is packaged in a 32 ld LQFP.
MPC9352 REVISION 8 MARCH 14, 2016
1
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