SN75061 Datasheet: Driver-Receiver Pair





SN75061 Driver-Receiver Pair Datasheet

Part Number SN75061
Description Driver-Receiver Pair
Manufacture etcTI
Total Page 13 Pages
PDF Download Download SN75061 Datasheet PDF

Features: ą • IEEE 802.3 1BASE5 Driver and Rece iver • On-Chip Receiver Squelch With Adjustable Threshold • Adjustable Squ elch Delay • Direct TTL-Level Squelch Output • Squelch Circuit Allows for External Noise Filtering • Two Driver -Enable Options • On-Chip Start-of-Id le Detection and Disable • Driver Pro vides 2-V Minimum into a 50-Ω Differe ntial Load Allowing for Use With Doubly -Terminated Lines and Multipoint Archit ectures • On-Chip Driver Slew-Rate Co ntrol for Very Closely Matched Output R ise and Fall Times SN75061 DRIVER/RECE IVER PAIR WITH SQUELCH ą SLLS026C − JANUARY 1987 − REVISED JULY 1990 N PA CKAGE (TOP VIEW) DRDLAJ DRO + DRO − SQDLAJ RXI + RXI − SQTHAJ GND 1 2 3 4 5 6 7 8 16 VCC 15 DATEN 14 DRI 13 DL EN 12 RXO 11 SQO 10 SQDLI 9 SQRXO DRIV ER INPUTS OUTPUTS DRI DATEN DLEN DRO + DRO − L LXLH H L XH L X HHZ Z H H L H† L† L H L L‡ H‡ Function Tables CONDITION No active signal ¶ Ac tive signal ¶ RECEIVER§ INPUTS RXI + RXI − XX LH HL OUTPUTS RXO SQO HH LL HL † This condition is vali.

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IEEE 802.3 1BASE5 Driver and Receiver
On-Chip Receiver Squelch With Adjustable
Threshold
Adjustable Squelch Delay
Direct TTL-Level Squelch Output
Squelch Circuit Allows for External Noise
Filtering
Two Driver-Enable Options
On-Chip Start-of-Idle Detection and Disable
Driver Provides 2-V Minimum into a 50-
Differential Load Allowing for Use With
Doubly-Terminated Lines and Multipoint
Architectures
On-Chip Driver Slew-Rate Control for Very
Closely Matched Output Rise and Fall
Times
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
ą
SLLS026C − JANUARY 1987 − REVISED JULY 1990
N PACKAGE
(TOP VIEW)
DRDLAJ
DRO +
DRO −
SQDLAJ
RXI +
RXI −
SQTHAJ
GND
1
2
3
4
5
6
7
8
16 VCC
15 DATEN
14 DRI
13 DLEN
12 RXO
11 SQO
10 SQDLI
9 SQRXO
DRIVER
INPUTS
OUTPUTS
DRI DATEN DLEN DRO + DRO −
L LXLH
H L XH L
X HHZ Z
H H L H† L†
L H L L‡ H‡
Function Tables
CONDITION
No active signal
Active signal
RECEIVER§
INPUTS
RXI + RXI −
XX
LH
HL
OUTPUTS
RXO SQO
HH
LL
HL
This condition is valid during the time period set by DRDLAJ following a rising transition on DRI. Following this, when a
subsequent positive transition does not occur on DRI, the outputs go to the high-impedance state.
This condition is valid when it occurs within the enable time set by DRDLAJ after a rising transition on DRI. Otherwise, the
outputs are in the high-impedance state.
§ Pins 9 and 10 are tied together.
An active signal is one that has an amplitude greater than the threshold level set by SQTHAJ.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1990, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
2−1

                    
                 






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