• IEEE 802.3 1BASE5 Driver and Receiver
• On-Chip Receiver Squelch With Adjustable
• Adjustable Squelch Delay
• Direct TTL-Level Squelch Output
• Squelch Circuit Allows for External Noise
• Two Driver-Enable Options
• On-Chip Start-of-Idle Detection and Disable
• Driver Provides 2-V Minimum into a 50-Ω
Differential Load Allowing for Use With
Doubly-Terminated Lines and Multipoint
• On-Chip Driver Slew-Rate Control for Very
Closely Matched Output Rise and Fall
DRIVER/RECEIVER PAIR WITH SQUELCH
SLLS026C − JANUARY 1987 − REVISED JULY 1990
DRI DATEN DLEN DRO + DRO −
H L XH L
X HHZ Z
H H L H† L†
L H L L‡ H‡
No active signal ¶
Active signal ¶
RXI + RXI −
† This condition is valid during the time period set by DRDLAJ following a rising transition on DRI. Following this, when a
subsequent positive transition does not occur on DRI, the outputs go to the high-impedance state.
‡ This condition is valid when it occurs within the enable time set by DRDLAJ after a rising transition on DRI. Otherwise, the
outputs are in the high-impedance state.
§ Pins 9 and 10 are tied together.
¶ An active signal is one that has an amplitude greater than the threshold level set by SQTHAJ.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1990, Texas Instruments Incorporated
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