Document
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• Each Device Drives 12 Lines • 60-V Output Voltage Swing Capability • 25-mA Output Source Current Capability • High-Speed Serially-Shifted Data Input • TTL-Compatible Inputs • Latches on All Driver Outputs
description
The SN65512B and SN75512B are monolithic BIDFET† integrated circuits designed to drive a dot matrix or segmented vacuum fluorescent display.
All device inputs are diode-clamped pnp inputs and assume a high logic level when open circuited. The nominal input threshold voltage is 1.5 V. Outputs are totem-pole structures formed by an npn emitter-follower and double-diffused MOS (DMOS) transistors.
The device consists of a 12-bit shift register, 12 latches, and 12 output AND gates. Serial data is entered into the shift register on the low-to-high transition of CLOCK. When high, LATCH ENABLE transfers the shift register contents to the outputs of the 12 latches. The active-low STROBE input enables all Q outputs. Serial data output from the shift register can be used to cascade shift registers. This output is not affected by LATCH ENABLE or STROBE.
The SN65512B is characterized for operation from − 40°C to 85°C. The SN75512B is characterized for operation from 0°C to 70°C.
SN65512B, SN75512B VACUUM FLUORESCENT DISPLAY DRIVERS
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SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
DW OR N PACKAGE (TOP VIEW)
Q11 Q12 STROBE SERIAL OUT DATA IN VCC1 CLOCK LATCH ENABLE
Q1 Q2
1 2 3 4 5 6 7 8 9 10
20 Q10 19 Q9 18 Q8 17 Q7 16 VCC2 15 GND 14 Q6 13 Q5 12 Q4 11 Q3
logic symbol‡
8 LATCH ENABLE
3 STROBE
7 CLOCK
TTL / VAC FLUOR DISPLAY
SRG12 C1/
5 DATA IN
2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3 2D 3
9 Q1
10 Q2
11 Q3
12 Q4
13 Q5
14 Q6
17 Q7
18 Q8
19 Q9
20 Q10
1 Q11
2 Q12
4 SERIAL OUT
‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
† BIDFET − Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1989, Texas Instruments Incorporated
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265 •POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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SN65512B, SN75512B VACUUM FLUORESCENT DISPLAY DRIVERS ą
SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
logic diagram (positive logic)
STROBE LATCH
ENABLE
DATA IN CLOCK
Shift Register
1D C1
R1
Latches
C2 LC1
2D
Q1
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1D C1
R2
C2 2D LC2
Q2
1D C2 R11 LC11
C1 2D
8 Stages (Q3 thru Q10)
Not Shown
Q11
1D C2 R12 LC12
C1 2D
Q12
SERIAL OUT
FUNCTION TABLE
FUNCTION
CONTROL INPUTS
CLOCK
LATCH ENABLE
STROBE
SHIFT REGISTER R1 THRU R12
LATCHES LC1 THRU LC12
SERIAL
OUTPUTS Q1 THRU Q12
Load
↑ No ↑
X
X
Load and shift† No change
Determined by LATCH ENABLE‡
R12 Determined by STROBE
Latch
X
L H
Stored data X As determined above New data
R12 Determined by STROBE
Strobe
X
X
H L
As determined above
Determined by LATCH ENABLE‡
R12
All LC LC1 thru LC12, respectively
H = high level, L = low level, X = irrelevant, ↑ = low-to-high-level transition † R12 takes on the state of R11, R11 takes on the state of R10, . . . R2 takes on the state of R1, and R1 takes on the state of the data input.
‡ New data enter the latches while LATCH ENABLE is high. These data are stored while LATCH ENABLE is low.
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•POST OFFICE BOX 655303 DALLAS, TEXAS 75265 •POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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typical operating sequence
CLOCK
SN65512B, SN75512B VACUUM FLUORESCENT DISPLAY DRIVERS
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SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
DATA IN
Valid
Irrelevant
SR Contents
LATCH ENABLE
Latch Contents
STROBE
Invalid Previously Stored Data
Valid New Data Valid
Q Outputs
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT VCC1
Valid
TYPICAL OF ALL OUTPUTS
OUT
VCC2 for Q Outputs
VCC1 for SERIAL OUT
Output
Input
GND
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265 •POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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SN65512B, SN75512B VACUUM FLUORESCENT DISPLAY DRIVERS ą
SLDS016A − DECEMBER 1985 − REVISED OCTOBER 1989
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Supply voltage, VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC1 Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Ope.