TIBPAL20R8-5C

TIBPAL20L8-5C, TIBPAL20R4-5C, TIBPAL20R6-5C, TIBPAL20R8-5C TIBPAL20L8-7M, TIBPAL20R4-7M, TIBPAL20R6-7M, TIBPAL20R8-7M HIGH-PERFORMANCE IMPACT-X ™ PAL® CIRCUITS SRPS010F – D3353, OCTOBER 1989 – REVISED SEPTEMBER 1992 High-Performance Operation: fmax (no feedback) TIBPAL20R’ -5C Series . . . 125 MHz Min TIBPAL20R’ -7M Series . . . 100 MHz Min fmax (internal feedback) TIBPAL20R’ -5C Series . . . 125 MHz Min TIBPAL20R’ -7M Series . . . 100 MHz Min fmax (external feedback) TIBPAL20R’ -5C Series . . . 117 MHz Min TIBPAL20R’ -7M Series . . . 74 MHz Min Propagation Delay TIBPAL20L8-5C Series . . . 5 ns Max TIBPAL20L8-7M Series . . . 7 ns Max TIBPAL20R’ -5C Series (CLK-to-Q) . . . 4 ns Max TIBPAL20R’ -7M Series (CLK-to-Q) . . . 6.5 ns Max Functionally Equivalent, but Faster Than, Existing 24-Pin PLDs Preload Capability on Output Registers Simplifies Testing Power-Up Clear on Registered Devices (All Register Outputs are Set Low, but Voltage Levels at the Output Pins Go High) Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs Security Fuse Prevents Duplication DEVICE I 3-STATE INPUTS O OUTPUTS PAL20L8 PAL20R4 PAL20R6 PAL20R8 14 12 12 12 2 0 0 0 REGISTERED Q OUTPUTS 0 4 (3-state buffers) 6 (3-state buffers) 8 (3-state buffers) I/O PORT S 6 4 2 0 description TIBPAL20L8’ C SUFFIX . . . JT OR NT PACKAGE M SUFFIX . . . JT PACKAGE (TOP VIEW) I I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 VCC 23 I 22 O 21 I/O...