TM2FJ64DPN Datasheet: EXTENDED-DATA-OUT DYNAMIC RAM MODULES





TM2FJ64DPN Datasheet PDF

Part Number TM2FJ64DPN
Description EXTENDED-DATA-OUT DYNAMIC RAM MODULES
Manufacture etcTI
Total Page 20 Pages
PDF Download Download TM2FJ64DPN Datasheet PDF

Features: TM2EJ64DPN, TM2FJ64DPN 2ā097ā152 BY 64 ĆBIT TM2EJ64EPN, TM2FJ64EPN 2ā097ā15 2 BY 64ĆBIT EXTENDEDĆDATAĆOUT DYNAMI C RAM MODULES Ċ SODIMM SMMS685 − AUG UST 1997 D Organization − TM2xJ64xPN -xx . . . 2 097 152 × 64 Bits D Singl e 3.3-V Power Supply (±10% Tolerance) D JEDEC 144-Pin Small Outline Dual-In- Line Memory Module (SODIMM) Without Bu ffer for Use With Socket D TM2xJ64xPN -xx — Utilizes Eight 16M-Bit (2M × 8-Bit) Dynamic RAMs in TSOPs D Perform ance ranges ACCESS ACCESS ACCESS TIME TIME TIME tRAC tCAC tAA MAX MAX MAX ED O CYCLE tHPC MIN ’2xJ64xPN-50 ’2xJ 64xPN-60 ’2xJ64xPN-70 50 ns 60 ns 70 ns 13 ns 15 ns 18 ns 25 ns 30 ns 35 ns 20 ns 25 ns 30 ns D High-Speed, Lo w-Noise LVTTL Interface D Long Refresh Period: − TM2EJ64DPN: 32 ms (2 048 cy cles) − TM2EJ64EPN: 64 ms (4 096 cycl es) D Low-Power, Battery-Backup Refresh Available: − TM2FJ64DPN: 128 ms (204 8 cycles) − TM2FJ64EPN: 128 ms (4 096 cycles) D 3-State Output D Extended-Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-On.

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TM2FJ64DPN datasheet
TM2EJ64DPN, TM2FJ64DPN 2ā097ā152 BY 64ĆBIT
TM2EJ64EPN, TM2FJ64EPN 2ā097ā152 BY 64ĆBIT
EXTENDEDĆDATAĆOUT DYNAMIC RAM MODULES Ċ SODIMM
SMMS685 − AUGUST 1997
D Organization
− TM2xJ64xPN-xx . . . 2 097 152 × 64 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D JEDEC 144-Pin Small Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
D TM2xJ64xPN-xx — Utilizes Eight 16M-Bit
(2M × 8-Bit) Dynamic RAMs in TSOPs
D Performance ranges
ACCESS ACCESS ACCESS
TIME TIME TIME
tRAC tCAC tAA
MAX MAX MAX
EDO
CYCLE
tHPC
MIN
’2xJ64xPN-50
’2xJ64xPN-60
’2xJ64xPN-70
50 ns
60 ns
70 ns
13 ns
15 ns
18 ns
25 ns
30 ns
35 ns
20 ns
25 ns
30 ns
D High-Speed, Low-Noise LVTTL Interface
D Long Refresh Period:
− TM2EJ64DPN: 32 ms (2 048 cycles)
− TM2EJ64EPN: 64 ms (4 096 cycles)
D Low-Power, Battery-Backup Refresh
Available:
− TM2FJ64DPN: 128 ms (2048 cycles)
− TM2FJ64EPN: 128 ms (4 096 cycles)
D 3-State Output
D Extended-Data-Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
D Serial Presence-Detect (SPD) Using
EEPROM
D Ambient Temperature Range
0°C to 70°C
D Gold-Plated Contacts
description
The TM2EJ64DPN is a 16M-byte, 144-pin, small outline dual-in-line memory module (SODIMM). The SODIMM
is composed of eight TMS427809A, 2 097 152 × 8-bit 2K-refresh EDO dynamic random-access memories
(DRAMs), each in a 400-mil, 28-pin plastic thin small-outline package (TSOP) (DGC suffix) mounted on a
substrate with decoupling capacitors. See the TMS427809A data sheet (literature number SMKS894).
The TM2EJ64EPN is an 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809A,
2 097 152 × 8-bit 4K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP (DGC suffix) mounted on a
substrate with decoupling capacitors. See the TMS426809A data sheet (literature number SMKS894).
The TM2FJ64DPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS427809AP,
2 097 152 × 8-bit 2K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809AP data sheet (literature
number SMKS894).
The TM2FJ64EPN is a 16M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS426809AP,
2 097 152 × 8-bit 4K low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP
(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS426809AP data sheet (literature
number SMKS894).
operation
The TM2xJ64xPN operates as eight TMS42x809A/Ps, connected as shown in the functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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