TM2SJ64EPN Datasheet: SYNCHRONOUS DYNAMIC RAM MODULES





TM2SJ64EPN SYNCHRONOUS DYNAMIC RAM MODULES Datasheet

Part Number TM2SJ64EPN
Description SYNCHRONOUS DYNAMIC RAM MODULES
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TM2SJ64EPN Datasheet PDF

Features: TM2SJ64EPN 2ā097ā152 BY 64ĆBIT SYNCHR ONOUS DYNAMIC RAM MODULES Ċ SODIMM D Organization: 2 097 152 x 64 Bits D Sin gle 3.3-V Power Supply (±10% Tolerance ) D Designed for 66-MHz 4-Clock Systems D JEDEC 144-Pin Small-Outline Dual-In- Line Memory Module (SODIMM) Without Buf fer for Use With Socket D Uses Eight 16 M-Bit Synchronous Dynamic RAMs (SDRAMs) (2M × 8-Bit) in Plastic Thin Small-Ou tline Packages (TSOP) D Byte-Read/Write Capability D Read Latencies 2 and 3 Su pported D Performance Ranges: SMMS697B − AUGUST 1997 − REVISED FEBRUARY 1 998 D Support Burst-Interleave and Burs t-Interrupt Operations D Burst Length P rogrammable to 1, 2, 4, and 8 D Two Ban ks for On-Chip Interleaving (Gapless Ac cess) D Ambient Temperature Range 0°C to 70°C D Gold-Plated Contacts D Pipel ine Architecture D High-Speed, Low-Nois e Low-Voltage TTL (LVTTL) Interface D S erial Presence Detect (SPD) Using EEPRO M ’2SJ64EPN-10 † CL = CAS latency SYNCHRONOUS CLOCK CYCLE TIME (CtLC=K33)† tCK2 (CL = 2) 10 ns 15 ns ACCE.

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TM2SJ64EPN 2ā097ā152 BY 64ĆBIT
SYNCHRONOUS DYNAMIC RAM MODULES Ċ SODIMM
D Organization: 2 097 152 x 64 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D Designed for 66-MHz 4-Clock Systems
D JEDEC 144-Pin Small-Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
D Uses Eight 16M-Bit Synchronous Dynamic
RAMs (SDRAMs) (2M × 8-Bit) in Plastic Thin
Small-Outline Packages (TSOP)
D Byte-Read/Write Capability
D Read Latencies 2 and 3 Supported
D Performance Ranges:
SMMS697B − AUGUST 1997 − REVISED FEBRUARY 1998
D Support Burst-Interleave and
Burst-Interrupt Operations
D Burst Length Programmable to 1, 2, 4,
and 8
D Two Banks for On-Chip Interleaving
(Gapless Access)
D Ambient Temperature Range
0°C to 70°C
D Gold-Plated Contacts
D Pipeline Architecture
D High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
D Serial Presence Detect (SPD) Using
EEPROM
’2SJ64EPN-10
CL = CAS latency
SYNCHRONOUS
CLOCK CYCLE
TIME
(CtLC=K33)
tCK2
(CL = 2)
10 ns
15 ns
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
tAC2
(CL = 3) (CL = 2)
7 ns 8 ns
REFRESH
INTERVAL
64 ms
description
The TM2SJ64EPN is a 16M-byte, 144-pin small-outline dual-in-line memory module (SODIMM). The SODIMM
is composed of eight TMS626812ADGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin
small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812A data
sheet (literature number SMOS691).
operation
The TM2SJ64EPN operates as eight TMS626812ADGE devices that are connected as shown in the
TM2SJ64EPN functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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