TM2SN64EPU Datasheet: SYNCHRONOUS DYNAMIC RAM MODULES





TM2SN64EPU SYNCHRONOUS DYNAMIC RAM MODULES Datasheet

Part Number TM2SN64EPU
Description SYNCHRONOUS DYNAMIC RAM MODULES
Manufacture etcTI
Total Page 16 Pages
PDF Download Download TM2SN64EPU Datasheet PDF

Features: D Organization: – TM2SN64EPU . . . 2 0 97 152 x 64 Bits – TM4SN64EPU . . . 4 194 304 x 64 Bits D Single 3.3-V Power Supply (±10% Tolerance) D Designed fo r 66-MHz 4-Clock Systems D JEDEC 168-Pi n Dual-In-Line Memory Module (DIMM) Wit hout Buffer for Use With Socket D TM2SN 64EPU — Uses Eight 16M-Bit Synchronou s Dynamic RAMs (SDRAMs) (2M × 8-Bit) i n Plastic Thin Small-Outline Packages ( TSOPs) D TM4SN64EPU — Uses Sixteen 16 M-Bit SDRAMs (2M × 8-Bit) in Plastic T SOPs D Byte-Read/Write Capability D Per formance Ranges: TM2SN64EPU 2097152 BY 64-BIT TM4SN64EPU 4194304 BY 64-BIT SY NCHRONOUS DYNAMIC RAM MODULES SMMS681 AUGUST 1997 D High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface D Rea d Latencies 2 and 3 Supported D Support Burst-Interleave and Burst-Interrupt O perations D Burst Length Programmable t o 1, 2, 4, and 8 D Two Banks for On-Chi p Interleaving (Gapless Access) D Ambie nt Temperature Range 0°C to 70°C D Go ld-Plated Contacts D Pipeline Architecture D Serial Presence-Detect (SPD) Usin.

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D Organization:
– TM2SN64EPU . . . 2 097 152 x 64 Bits
– TM4SN64EPU . . . 4 194 304 x 64 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D Designed for 66-MHz 4-Clock Systems
D JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
D TM2SN64EPU — Uses Eight 16M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(2M × 8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
D TM4SN64EPU — Uses Sixteen 16M-Bit
SDRAMs (2M × 8-Bit) in Plastic TSOPs
D Byte-Read/Write Capability
D Performance Ranges:
TM2SN64EPU 2097152 BY 64-BIT
TM4SN64EPU 4194304 BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS681 – AUGUST 1997
D High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
D Read Latencies 2 and 3 Supported
D Support Burst-Interleave and
Burst-Interrupt Operations
D Burst Length Programmable to 1, 2, 4,
and 8
D Two Banks for On-Chip Interleaving
(Gapless Access)
D Ambient Temperature Range
0°C to 70°C
D Gold-Plated Contacts
D Pipeline Architecture
D Serial Presence-Detect (SPD) Using
EEPROM
’xSN64EPU-12A
SYNCHRONOUS
CLOCK CYCLE
TIME
(CtLC=K33)
tCK2
(CL = 2)
12 ns
15 ns
ACCESS TIME
CLOCK TO
OUTPUT
tCK3
tCK2
(CL = 3) (CL = 2)
9 ns 9 ns
REFRESH
INTERVAL
64 ms
’xSN64EPU-12
12 ns 18 ns 9 ns 10 ns
CL = CAS latency
‡ –12A speed device is supported only at –5 to +10% VDD
64 ms
description
The TM2SN64EPU is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of
eight TMS626812DGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number
SMOS687).
The TM4SN64EPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812DGE,
2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors. See the TMS626812 data sheet (literature number SMOS687).
operation
The TM2SN64EPU operates as eight TMS626812DGE devices that are connected as shown in the
TM2SN64EPU functional block diagram. The TM4SN64EPU operates as 16 TMS626812DGE devices
connected as shown in the TM4SN64EPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1997, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1

                    
                    






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