TM4SR72EPN Datasheet: SYNCHRONOUS DYNAMIC RAM MODULES





TM4SR72EPN Datasheet PDF

Part Number TM4SR72EPN
Description SYNCHRONOUS DYNAMIC RAM MODULES
Manufacture etcTI
Total Page 15 Pages
PDF Download Download TM4SR72EPN Datasheet PDF

Features: TM2SR72EPN 2ā097ā152 BY 72ĆBIT TM4SR7 2EPN 4ā194ā304 BY 72ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998 D Organ ization − TM2SR72EPN . . . 2 097 152 x 72 Bits − TM4SR72EPN . . . 4 194 30 4 x 72 Bits D Single 3.3-V Power Supply (±10% Tolerance) D Designed for 66-MH z 4-Clock Systems D JEDEC 168-Pin Dual- In-Line Memory Module (DIMM) Without Bu ffer for Use With Socket D TM2SR72EPN Uses Nine 16M-Bit Synchronous Dynami c RAMs (SDRAMs) (2M × 8-Bit) in Plasti c Thin Small-Outline Packages (TSOPs) D TM4SR72EPN — Uses 18 16M-Bit SDRAMs (2M × 8-Bit) in Plastic TSOPs D Perfor mance Ranges: D D D D D D D D D D SYN CHRONOUS CLOCK CYCLE TIME tCK3 tCK2 (CL = 3)† (CL = 2) ’xSR72EPN-10 10 ns † CL = CAS latency 15 ns AC CESS TIME (CLOCK TO OUTPUT) tAC3 tA C2 (CL = 3) (CL = 2) 7.5 ns 7 ns RE FRESH INTERVAL 64 ms High-Speed, Low-N oise Low-Voltage TTL (LVTTL) Interface Byte-Read/Write Capability Read Latencies 2 and 3 Supported Support Burst-Interleave and B.

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TM4SR72EPN datasheet
TM2SR72EPN 2ā097ā152 BY 72ĆBIT
TM4SR72EPN 4ā194ā304 BY 72ĆBIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS698A − JUNE 1997 − REVISED FEBRUARY 1998
D Organization
− TM2SR72EPN . . . 2 097 152 x 72 Bits
− TM4SR72EPN . . . 4 194 304 x 72 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D Designed for 66-MHz 4-Clock Systems
D JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
D TM2SR72EPN — Uses Nine 16M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(2M × 8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
D TM4SR72EPN — Uses 18 16M-Bit SDRAMs
(2M × 8-Bit) in Plastic TSOPs
D Performance Ranges:
D
D
D
D
D
D
D
D
D
D
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
(CL = 3)† (CL = 2)
’xSR72EPN-10
10 ns
CL = CAS latency
15 ns
ACCESS TIME
(CLOCK TO
OUTPUT)
tAC3
tAC2
(CL = 3) (CL = 2)
7.5 ns
7 ns
REFRESH
INTERVAL
64 ms
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Byte-Read/Write Capability
Read Latencies 2 and 3 Supported
Support Burst-Interleave and
Burst-Interrupt Operations
Burst Length Programmable to 1, 2, 4,
and 8
Two Banks for On-Chip Interleaving
(Gapless Access)
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Pipeline Architecture
Serial Presence Detect (SPD) Using
EEPROM
description
The TM2SR72EPN is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of nine
TMS626812ADGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812A data sheet (literature
number SMOS691).
The TM4SR72EPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812ADGE,
2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors. See the TMS626812A data sheet (literature number SMOS691).
operation
The TM2SR72EPN operates as nine TMS626812ADGE devices that are connected as shown in the
TM2SR72EPN functional block diagram. The TM4SR72EPN operates as eighteen TMS626812ADGE devices
connected as shown in the TM4SR72EPN functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1

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