TM4SR72EPU Datasheet: SYNCHRONOUS DYNAMIC RAM MODULES





TM4SR72EPU SYNCHRONOUS DYNAMIC RAM MODULES Datasheet

Part Number TM4SR72EPU
Description SYNCHRONOUS DYNAMIC RAM MODULES
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TM4SR72EPU Datasheet PDF

Features: TM2SR72EPU 2ā097ā152 BY 72ĆBIT TM4SR7 2EPU 4ā194ā304 BY 72ĆBIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS683A − JUNE 1997 − REVISED AUGUST 1997 D Organiz ation − TM2SR72EPU . . . 2 097 152 x 72 Bits − TM4SR72EPU . . . 4 194 304 x 72 Bits D Single 3.3-V Power Supply ( ±10% Tolerance) D Designed for 66-MHz 4-Clock Systems D JEDEC 168-Pin Dual-In -Line Memory Module (DIMM) Without Buff er for Use With Socket D TM2SR72EPU — Uses Nine 16M-Bit Synchronous Dynamic RAMs (SDRAMs) (2M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) D T M4SR72EPU — Uses 18 16M-Bit SDRAMs (2 M × 8-Bit) in Plastic TSOPs D Performa nce Ranges: D D D D D D D D D D ’xS R72EPU-12A‡ SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 (CL = 3)† (CL = 2) 12 ns 15 ns ACCESS TIME (CLOCK TO OUTPUT) tCK3 tCK2 (CL = 3) (CL = 2) 9 ns 9 ns REFRESH INTERVAL 64 ms ’ xSR72EPU-12 12 ns 18 ns 9 ns 10 ns † CL = CAS latency ‡ -12A speed de vice is supported only at −5% to +10% VDD 64 ms High-Speed, Low-Noise Low-Voltage TTL (LVTTL) .

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TM2SR72EPU 2ā097ā152 BY 72ĆBIT
TM4SR72EPU 4ā194ā304 BY 72ĆBIT
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS683A − JUNE 1997 − REVISED AUGUST 1997
D Organization
− TM2SR72EPU . . . 2 097 152 x 72 Bits
− TM4SR72EPU . . . 4 194 304 x 72 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D Designed for 66-MHz 4-Clock Systems
D JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
D TM2SR72EPU — Uses Nine 16M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(2M × 8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
D TM4SR72EPU — Uses 18 16M-Bit SDRAMs
(2M × 8-Bit) in Plastic TSOPs
D Performance Ranges:
D
D
D
D
D
D
D
D
D
D
’xSR72EPU-12A
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
(CL = 3)† (CL = 2)
12 ns
15 ns
ACCESS TIME
(CLOCK TO
OUTPUT)
tCK3
tCK2
(CL = 3) (CL = 2)
9 ns 9 ns
REFRESH
INTERVAL
64 ms
’xSR72EPU-12
12 ns
18 ns
9 ns
10 ns
CL = CAS latency
‡ -12A speed device is supported only at −5% to +10% VDD
64 ms
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Byte-Read/Write Capability
Read Latencies 2 and 3 Supported
Support Burst-Interleave and
Burst-Interrupt Operations
Burst Length Programmable to 1, 2, 4,
and 8
Two Banks for On-Chip Interleaving
(Gapless Access)
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Pipeline Architecture
Serial Presence-Detect (SPD) Using
EEPROM
description
The TM2SR72EPU is a 16M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of nine
TMS626812DGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic thin small-outline package
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS626812 data sheet (literature number
SMOS687).
The TM4SR72EPU is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812DGE,
2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors. See the TMS626812 data sheet (literature number SMOS687).
operation
The TM2SR72EPU operates as nine TMS626812DGE devices that are connected as shown in the
TM2SR72EPU functional block diagram. The TM4SR72EPU operates as eighteen TMS626812DGE devices
connected as shown in the TM4SR72EPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1

                    
                    






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