TM8SK64JPU Datasheet: SYNCHRONOUS DYNAMIC RAM MODULES





TM8SK64JPU SYNCHRONOUS DYNAMIC RAM MODULES Datasheet

Part Number TM8SK64JPU
Description SYNCHRONOUS DYNAMIC RAM MODULES
Manufacture etcTI
Total Page 13 Pages
PDF Download Download TM8SK64JPU Datasheet PDF

Features: TM8SK64JPU 8ā388ā608 BY 64ĆBIT SYNCHR ONOUS DYNAMIC RAM MODULE Ċ SODIMM D O rganization: − TM8SK64JPU . . . 8 388 608 x 64 Bits D Single 3.3-V Power Sup ply (±10% Tolerance) D Designed for 66 -MHz 4-Clock Systems D JEDEC 144-Pin Sm all Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With So cket D Uses Eight 64M-Bit Synchronous D ynamic RAMs (SDRAMs) (8M × 8-Bit) in P lastic Thin Small-Outline Packages (TSO Ps) D Byte-Read/Write Capability D Perf ormance Ranges: D High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface SMM S690B − AUGUST 1997 − REVISED FEBRU ARY 1998 D Read Latencies 2 and 3 Suppo rted D Support Burst-Interleave and Bur st-Interrupt Operations D Burst Length Programmable to 1, 2, 4, and 8 D Four B anks for On-Chip Interleaving (Gapless Access) D Ambient Temperature Range 0° C to 70°C D Gold-Plated Contacts D Pip eline Architecture D Serial Presence De tect (SPD) Using EEPROM ’8SK64JPU-10 SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 10 ns 15 ns ACCESS TIME CLOCK TO .

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TM8SK64JPU 8ā388ā608 BY 64ĆBIT
SYNCHRONOUS DYNAMIC RAM MODULE Ċ SODIMM
D Organization:
− TM8SK64JPU . . . 8 388 608 x 64 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D Designed for 66-MHz 4-Clock Systems
D JEDEC 144-Pin Small Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
D Uses Eight 64M-Bit Synchronous Dynamic
RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin
Small-Outline Packages (TSOPs)
D Byte-Read/Write Capability
D Performance Ranges:
D High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998
D Read Latencies 2 and 3 Supported
D Support Burst-Interleave and
Burst-Interrupt Operations
D Burst Length Programmable to
1, 2, 4, and 8
D Four Banks for On-Chip Interleaving
(Gapless Access)
D Ambient Temperature Range
0°C to 70°C
D Gold-Plated Contacts
D Pipeline Architecture
D Serial Presence Detect (SPD) Using
EEPROM
’8SK64JPU-10
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
10 ns
15 ns
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
tAC2
8 ns 9 ns
REFRESH
INTERVAL
tREF
64 ms
description
The TM8SK64JPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664814DGE,
8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a
substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS690).
operation
The TM8SK64JPU operates as eight TMS664814DGE devices that are connected as shown in the
TM8SK64JPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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