TM8TT64JPN

PRODUCT PREVIEW TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES SMMS700A − APRIL 1998 − REVISED AUGUST 1998 D Organization: − TM8TT64JPN . . . 8 388 608 × 64 Bits − TM16TT64JPN . . . 16 777 216 × 64 Bits − TM8TT72JPN . . . 8 388 608 × 72 Bits − TM16TT72JPN . . . 16 777 216 × 72 Bits D Designed for 100-MHz 4-Clock Systems D JEDEC 168-Pin Dual-In-Line Memory Module (DIMM) Without Buffer for Use With Socket D TM8TT64JPN — Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) D TM16TT64JPN — Uses Sixteen 64M-Bit SDRAMs (8M × 8-Bit) in Plastic TSOPs D TM8TT72JPN — Uses Nine 64M-Bit SDRAMs (8M × 8-Bit) in Plastic TSOPs D TM16TT72JPN — Uses Eighteen 64M-Bit SDRAMs (8M × 8-Bit) in Plastic TSOPs D Performance Ranges: D Single 3.3-V Power Supply (±10% Tolerance) D Byte-Read/Write Capability D High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface D Read Latencies 2 and 3 Supported D Supports Burst-Interleave and Burst-Interrupt Operations D Burst Length Programmable to 1, 2, 4, and 8 D Four Banks for On-Chip Interleaving (Gapless Access) D Ambient Temperature Range 0°C to 70°C D Gold-Plated Contacts D Pipeline Architecture D Serial Presence-Detect (SPD) Using EEPROM ’xTTxxJPN-8 ’xTTxxJPN-8A SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 8 ns 10 ns 8 ns 10 ns ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 6 ns 6 ns 6 ns 7.5 ns REFRESH INTERVAL tREF 64 ms 64 ms description The TM8TT64JPN is a 64M-b...