Document
PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A − APRIL 1998 − REVISED AUGUST 1998
D Organization:
− TM8TT64JPN . . . 8 388 608 × 64 Bits − TM16TT64JPN . . . 16 777 216 × 64 Bits − TM8TT72JPN . . . 8 388 608 × 72 Bits − TM16TT72JPN . . . 16 777 216 × 72 Bits
D Designed for 100-MHz 4-Clock Systems D JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With Socket
D TM8TT64JPN — Uses Eight 64M-Bit
Synchronous Dynamic RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs)
D TM16TT64JPN — Uses Sixteen 64M-Bit
SDRAMs (8M × 8-Bit) in Plastic TSOPs
D TM8TT72JPN — Uses Nine 64M-Bit
SDRAMs (8M × 8-Bit) in Plastic TSOPs
D TM16TT72JPN — Uses Eighteen 64M-Bit
SDRAMs (8M × 8-Bit) in Plastic TSOPs
D Performance Ranges:
D Single 3.3-V Power Supply
(±10% Tolerance)
D Byte-Read/Write Capability D High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
D Read Latencies 2 and 3 Supported D Supports Burst-Interleave and
Burst-Interrupt Operations
D Burst Length Programmable to 1, 2, 4,
and 8
D Four Banks for On-Chip Interleaving
(Gapless Access)
D Ambient Temperature Range
0°C to 70°C
D Gold-Plated Contacts D Pipeline Architecture D Serial Presence-Detect (SPD) Using
EEPROM
’xTTxxJPN-8 ’xTTxxJPN-8A
SYNCHRONOUS CLOCK CYCLE
TIME
tCK3
tCK2
8 ns 10 ns
8 ns 10 ns
ACCESS TIME CLOCK TO OUTPUT
tAC3
tAC2
6 ns 6 ns
6 ns 7.5 ns
REFRESH INTERVAL
tREF 64 ms 64 ms
description
The TM8TT64JPN is a 64M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of eight TMS664814ADGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
The TM16TT64JPN is a 128M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS664814ADGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
The TM8TT72JPN is a 64M-byte, 168-pin DIMM. The DIMM is composed of nine TMS664814ADGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
The TM16TT72JPN is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS664814ADGE, 2 097 152 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright 1998, Texas Instruments Incorporated
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PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A − APRIL 1998 − REVISED AUGUST 1998
operation The TM8TT64JPN operates as eight TMS664814DGE devices that are connected as shown in the TM8TT64JPN functional block diagram. The TM16TT64JPN operates as 16 TMS664814ADGE devices connected as shown in the TM16TT64JPN functional block diagram. The TM8TT72JPN operates as nine TMS664814ADGE devices that are connected as shown in the TM8TT72JPN functional block diagram. The TM16TT72JPN operates as 18 TMS664814ADGE devices connected as shown in the TM16TT72JPN functional block diagram.
•2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
DUAL-IN-LINE MEMORY MODULE ( TOP VIEW )
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TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A − APRIL 1998 − REVISED AUGUST 1998
TM8TT64JPN TM16TT64JPN ( SIDE VIEW ) ( SIDE VIEW )
PIN NOMENCLATURE
A[0:11] A[0:8] A13/BA0 A12/BA1 CAS CB[0:7] CKE[0:1] CK[0:3] DQ[0:63] DQMB[0:7]
NC RAS S[0:3] SA[0:2]
SCL SDA VDD VSS WE WP
Row Address Inputs Column Address Inputs Bank-Select Zero Bank-Select One Column-Address Strobe Check Bit In/Check Bit Out Clock Enable System Clock Data-In / Data-Out Data-In/Data-Out Mask Enable No Connect Row-Address Strobe Chip-Select Serial Presence-Detect (SPD) Device Address Input SPD Clock SPD Address / Data 3.3-V Supply Ground Write Enable Write Protect
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PRODUCT PREVIEW
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•POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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PRODUCT PREVIEW
TM8TT64JPN, TM16TT64JPN TM8TT72JPN, TM16TT72JPN SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A − APRIL 1998 − REVISED AUGUST 1998
Pin Assignments
PIN NO. NAME
1 VSS 2 DQ0 3 DQ1 4 DQ2 5 DQ3 6 VDD 7 DQ4 8 DQ5 9 DQ6 10 DQ7 11.