TM8TU72JPW Datasheet: SYNCHRONOUS DYNAMIC RAM MODULES





TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODULES Datasheet

Part Number TM8TU72JPW
Description SYNCHRONOUS DYNAMIC RAM MODULES
Manufacture etcTI
Total Page 26 Pages
PDF Download Download TM8TU72JPW Datasheet PDF

Features: TM8TU72JPW SYNCHRONOUS DYNAMIC RAM MODUL E D Organization: − TM8TU72JPW . . . 8 388 608 × 72 Bits D Designed for 10 0-MHz, 72-Bit 4-Clock Systems D JEDEC 1 68-Pin Dual-In-Line Memory Module (DIMM ) With Register for Use With Socket D T M8TU72JPW — Uses Nine 64M-Bit (8M × 8-Bit) SDRAMs in Plastic Thin Small-Out line Package (TSOP), Two SN74ALVC162836 20-Bit Universal Bus Drivers in Thin S hrink Small-Outline Package (TSSOP), an d One CDC2510 Phase-Lock Loop (PLL) in TSSOP D Single 3.3-V Power Supply (±10 % Tolerance) D Performance Ranges: SMM S713 − JUNE 1998 D Byte-Read/Write Ca pability D High-Speed, Low-Noise, Low-V oltage TTL (LVTTL) Interface D Read Lat encies 2 and 3 Supported D Supports Bur st-Interleave and Burst-Interrupt Opera tions D Burst Length Programmable to 1, 2, 4, and 8 D Four Banks for On-Chip I nterleaving (Gapless Access) D Ambient Temperature Range 0°C to 70°C D Gold- Plated Contacts D Pipeline Architecture D Serial Presence-Detect (SPD) Using EEPROM ’8TU72JPW-8 ’8TU72JPW-8A SY.

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TM8TU72JPW
SYNCHRONOUS DYNAMIC RAM MODULE
D Organization:
− TM8TU72JPW . . . 8 388 608 × 72 Bits
D Designed for 100-MHz, 72-Bit 4-Clock
Systems
D JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) With Register for Use With
Socket
D TM8TU72JPW — Uses Nine 64M-Bit
(8M × 8-Bit) SDRAMs in Plastic Thin
Small-Outline Package (TSOP), Two
SN74ALVC162836 20-Bit Universal Bus
Drivers in Thin Shrink Small-Outline
Package (TSSOP), and One CDC2510
Phase-Lock Loop (PLL) in TSSOP
D Single 3.3-V Power Supply
(±10% Tolerance)
D Performance Ranges:
SMMS713 − JUNE 1998
D Byte-Read/Write Capability
D High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
D Read Latencies 2 and 3 Supported
D Supports Burst-Interleave and
Burst-Interrupt Operations
D Burst Length Programmable to 1, 2, 4,
and 8
D Four Banks for On-Chip Interleaving
(Gapless Access)
D Ambient Temperature Range
0°C to 70°C
D Gold-Plated Contacts
D Pipeline Architecture
D Serial Presence-Detect (SPD) Using
EEPROM
’8TU72JPW-8
’8TU72JPW-8A
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
8 ns 10 ns
8 ns 10 ns
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
tAC2
6 ns 6 ns
6 ns 7.5 ns
REFRESH
INTERVAL
tREF
64 ms
64 ms
description
The TM8TU72JPW is a 64M-byte, 168-pin registered dual-in-line memory module (DIMM). The registered
DIMM is composed of nine TMS664814DGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin
small-outline package (TSOP); two SN74ALVC162836DGG, 20-bit universal bus drivers, each in a 240-mil,
56-pin thin shrink small-outline package (TSSOP); and one CDC2510 phase-lock loop (PLL) in a 177-mil, 24-pin
TSSOP mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number
SMOS695), the SN74ALVC162836 data sheet (literature number SCES129), and the CDC2510 data sheet
(literature number SCAS597) for reference.
operation
The TM8TU72JPW operates as nine TMS664814DGE devices that are connected as shown in the
TM8TU72JPW functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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