Document
• EIA-170 Timing Operation • Solid-State Reliability • Fixed Electronic-Shutter Options • Random Shutter-Mode • Flicker-Compensation Mode
TMC57750 1/4-INCH RS-170 TIMER
SOCS041 – JUNE 1994
• Auto-Iris Capability • Electronic-Windowing Options • Horizontal and Vertical Resets for External
Synchronization
• Double-Speed Readout Option
FI VD HD V CC PUC SCAN CLKN XIN XOUT XSEL MCLK/2 MCLK/4 GND CDS S/H SHTMON
SRGSEL PHSEL1 PHSEL2
DSEL SRM SRG GND SAG IAG2 IAG1 VCC ABM ABG
ABGSEL
FSSEL DSSEL
48 4746 45 44 43 42 4140 39 38 37 36 35 34 33
49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VACT SHTCOM HR VR SSEL3 SSEL2 VCC SSEL1 CPOB2 CPOB1 GND CSYNC
CBLK TEST4 EU ED
TEST1 TEST2 TEST3
GND MON1 MON2 MON3 MON4 EFSEL1 EFSEL2 EFSEL3 MINSEL
VCC WSEL1 WSEL2 WINDOW
description
The TMC57750 is a monolithic integrated circuit designed to supply timing signals for the Texas Instruments (TI™) 4-mm TC255 monochrome CCD image sensor. The TMC57750 supplies both CCD drive signals and EIA-170 television-synchronization signals at standard video rates. It requires a single 5-V supply voltage and a 25-MHz timing crystal or crystal oscillator. The TMC57750 provides the user with several options including antiblooming-frequency selection, external synchronization, fixed electronic-shutter selection, electronic auto-iris, and window selection.
The TMC57750 is designed to drive the TC255 CCD image sensor through an intermediary level-shifting device such as the TI TMC57253 serial and parallel driver. It supplies sampling, clamping, and synchronizing signals for the TI SN76121OFR video processor. The TMC57750 EIA-170 synchronization signals include composite sync, composite blank, and field indicator.
The TMC57750 is supplied in a 64-pin plastic flat package and is characterized for operation from –20°C to 45°C.
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1994, Texas Instruments Incorporated 1
TMC57750 1/4-INCH RS-170 TIMER
SOCS041 – JUNE 1994
functional block diagram
VCC GND CLKIN XSEL
XIN XOUT PHSEL1 PHSEL2 DSEL
HR VR ED EU ABGSEL DSSEL EFSEL1 EFSEL2 EFSEL3 FSSEL MINSEL SHTCOM SRGSEL SSEL1 SSEL2 SSEL3 WSEL1 WSEL2 PUC
13, 26, 45, 59 4, 22, 36, 55
42 39
25-MHz 41 Oscillator 40 50 51 52 30 29 17 18 62 64 9 10 11 63 12
Mode 31 Select 49 25 27 28 14 15 44
Divide by 4 Divide by 2 Serial Counter
Horizontal Counter
Vertical Counter
Iris Counter
Iris Controller
Mode Select
37 38
35 54 34 53
Decoder
61 60 20 23 24 21 448 46 58 57 56 33 32 47 16
MCLK/4
MCLK/2
CDS SRG S/H SRM
ABG ABM CBLK CPOB1 CPOB2 CSYNC FI HD IAG1 IAG2 SAG SHTMON VACT VD WINDOW
•2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TERMINAL
NAME
NO.
ABG
61
ABM
60
ABGSEL
62
CLKIN CBLK CPOB1 CPOB2 CSYNC CDS
DSEL
42 20 23 24 21 35
52
DSSEL
64
ED EU EFSEL1, EFSEL2, EFSEL3 FI
FSSEL
GND
HD HR IAG1 IAG2 MCLK/4 MCLK/2
MINSEL
MON1, MON2, MON3, MON4
17 18
9, 10, 11
49
63
4, 22, 36, 55 46 30 58 57 37 38
12
5, 6, 7, 8
PHSEL1, PHSEL2
50, 51
Terminal Functions
TMC57750 1/4-INCH RS-170 TIMER
SOCS041 – JUNE 1994
I/O DESCRIPTION
O Antiblooming gate
O Antiblooming gate mid-level
Antiblooming-gate select. ABGSEL selects the frequency of the antiblooming gate. When ABGSEL I is high, the standard frequency of 6.25 MHz is selected. When low, the double frequency of 12.5
MHz is selected.
I Clock in
O Composite blank
O Optical black clamp one
O Optical black clamp two
O Composite sync
O Co9rrelated double sampling
Delay select. DSEL selects the delay of CDS and S/H with respect to SRG. When DSEL is high, I a standard delay is selected. When low, an additional delay of 5 ns is selected.
Display-scan select. DSSEL selects the display-scanning mode. When DSSEL is high, the interlace
I
mode is selected. When low, the noninterlace mode is selected. In the interlace mode, one field is 262.5 horizontal lines and one frame is 525 horizontal lines. In the noninterlace mode, one field is
262 horizontal lines and one frame is 524 horizontal lines.
I Exposure down. ED decreases the integration of the CCD sensor.
I Exposure up. EU increases the integration of the CCD sensor.
I
Electronic-function select. EFSEL1, EFSEL2, and EFSEL3 selects the operational modes (see Table 1 and Figure 4).
O Field index
I
Frame-shift select. FSSEL selects the parallel-transfer frequency. When FSSEL is high, the standard frequency of 12.5 MHz is selected. When low, the double frequency of 25 MHz is selected.
Ground
O Horizontal drive
I Horizontal reset
O Image-area gate 1
O Image-area gate 2
O Master clock divided by 4
O Master clock divided by 2
Minimum exposure-tim.