TMS27PC210A Datasheet: Programmable ROM





TMS27PC210A Programmable ROM Datasheet

Part Number TMS27PC210A
Description Programmable ROM
Manufacture etcTI
Total Page 29 Pages
PDF Download Download TMS27PC210A Datasheet PDF

Features: D Organization . . . 65 536 by 16 Bits D Single 5-V Power Supply D Operationall y Compatible With Existing Megabit EPRO Ms D 40-Pin Dual-In-Line Package and 44 -Lead Plastic Leaded Chip Carrier D All Inputs / Outputs Fully TTL Compatible D ±10% VCC Tolerance D Maximum Access / Minimum Cycle Time ’27C/PC210A-10 1 00 ns ’27C/ PC210A-12 120 ns ’27C/ PC210A-15 150 ns ’27C/ PC210A-20 200 ns ’27C/ PC210A-25 250 ns D 16-Bit Ou tput For Use in Microprocessor-Based Sy stems D Very High-Speed SNAP! Pulse Pro gramming D Power-Saving CMOS Technology D 3-State Output Buffers D 400-mV Mini mum DC Noise Immunity With Standard TTL Loads D Latchup Immunity of 250 mA on All Input and Output Pins D No Pullup R esistors Required D Low Power Dissipati on − Active . . . 275 mW Worst Case Standby . . . 0.55 mW Worst Case (CM OS-Input Levels) D Temperature Range Op tions PIN NOMENCLATURE A0 −A15 DQ0 −DQ15 E G GND NC PGM VCC VPP Address Inputs Inputs (programming) / Outputs Chip Enable Output Enable Ground No Interna.

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D Organization . . . 65 536 by 16 Bits
D Single 5-V Power Supply
D Operationally Compatible With Existing
Megabit EPROMs
D 40-Pin Dual-In-Line Package and 44-Lead
Plastic Leaded Chip Carrier
D All Inputs / Outputs Fully TTL Compatible
D ±10% VCC Tolerance
D Maximum Access / Minimum Cycle Time
’27C/PC210A-10 100 ns
’27C/ PC210A-12 120 ns
’27C/ PC210A-15 150 ns
’27C/ PC210A-20 200 ns
’27C/ PC210A-25 250 ns
D 16-Bit Output For Use in
Microprocessor-Based Systems
D Very High-Speed SNAP! Pulse
Programming
D Power-Saving CMOS Technology
D 3-State Output Buffers
D 400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D Latchup Immunity of 250 mA on All Input
and Output Pins
D No Pullup Resistors Required
D Low Power Dissipation
− Active . . . 275 mW Worst Case
− Standby . . . 0.55 mW Worst Case
(CMOS-Input Levels)
D Temperature Range Options
PIN NOMENCLATURE
A0 −A15
DQ0 −DQ15
E
G
GND
NC
PGM
VCC
VPP
Address Inputs
Inputs (programming) / Outputs
Chip Enable
Output Enable
Ground
No Internal Connection
Program
5-V Power Supply
13-V Power Supply‡
Pins 11 and 30 (J package) and pins 12 and 34 (FN
package) must be connected externally to ground.
Only in program mode
TMS27C210A 65536 BY 16ĆBIT UV ERASABLE
TMS27PC210A 65536 BY 16ĆBIT
PROGRAMMABLE READĆONLY MEMORIES
SMLS310D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
J PACKAGE
( TOP VIEW )
VPP
E
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
GND†
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 PGM
38 NC
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND†
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
FN PACKAGE
( TOP VIEW )
DQ12
DQ11
DQ10
DQ9
DQ8
GND†
NC
DQ7
DQ6
DQ5
DQ4
6543
7
8
9
10
11
12
13
14
15
16
17
2 1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
GND†
NC
A8
A7
A6
A5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1

                    
                    






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