TMS28F200BZT Datasheet: BOOT-BLOCK FLASH MEMORIES





TMS28F200BZT BOOT-BLOCK FLASH MEMORIES Datasheet

Part Number TMS28F200BZT
Description BOOT-BLOCK FLASH MEMORIES
Manufacture etcTI
Total Page 29 Pages
PDF Download Download TMS28F200BZT Datasheet PDF

Features: D Organization . . . 262144 by 8 bit s 1 31 072 by 16 bits D Array-Blocking Arch itecture – Two 8K-Byte Parameter Bloc ks – One 96K-Byte Main Block – One 128K-Byte Main Block – One 16K-Byte P rotected Boot Block – Top or Bottom B oot Locations D All Inputs / Outputs TT L Compatible D Maximum Access / Minimum Cycle Time VCC ± 10% ’28F200BZx70 7 0 ns ’28F200BZx80 80 ns ’28F200BZx9 0 90 ns (x = top (T) or bottom (B) boot -block configurations ordered) D 10000 Program / Erase-Cycles D Three Temperat ure Ranges – Commercial . . . 0°C to 70°C – Extended . . . – 40°C to 85°C – Automotive . . . – 40°C to 125°C D Low Power Dissipation ( VCC = 5.5 V ) – Active Write . . . 330 mW ( Byte-Write) – Active Read . . . 330 mW ( Byte-Read) – Active Write . . . 358 mW ( Word-Write) – Active Read . . . 330 mW ( Word-Read) – Block-Eras e . . . 165 mW – Standby . . . 0.55 m W (CMOS-Input Levels) – Deep Power-Do wn Mode . . . 0.0066 mW D Fully Automated On-Chip Erase and Word / Byte-Program Operations D Write-Protection .

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D Organization . . . 262144 by 8 bit s
131 072 by 16 bits
D Array-Blocking Architecture
– Two 8K-Byte Parameter Blocks
– One 96K-Byte Main Block
– One 128K-Byte Main Block
– One 16K-Byte Protected Boot Block
– Top or Bottom Boot Locations
D All Inputs / Outputs TTL Compatible
D Maximum Access / Minimum Cycle Time
VCC ± 10%
’28F200BZx70 70 ns
’28F200BZx80 80 ns
’28F200BZx90 90 ns
(x = top (T) or bottom (B) boot-block
configurations ordered)
D 10000 Program / Erase-Cycles
D Three Temperature Ranges
– Commercial . . . 0°C to 70°C
– Extended . . . – 40°C to 85°C
– Automotive . . . – 40°C to 125°C
D Low Power Dissipation ( VCC = 5.5 V )
– Active Write . . . 330 mW ( Byte-Write)
– Active Read . . . 330 mW ( Byte-Read)
– Active Write . . . 358 mW ( Word-Write)
– Active Read . . . 330 mW ( Word-Read)
– Block-Erase . . . 165 mW
– Standby . . . 0.55 mW (CMOS-Input
Levels)
– Deep Power-Down Mode . . . 0.0066 mW
D Fully Automated On-Chip Erase and
Word / Byte-Program Operations
D Write-Protection for Boot Block
D Industry-Standard Command State Machine
(CSM)
– Erase-Suspend/Resume
– Algorithm-Selection Identifier
TMS28F200BZT, TMS28F200BZB
262144 BY 8-BIT/131072 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS200E – JUNE 1994 – REVISED JANUARY 1998
DBJ PACKAGE
( TOP VIEW )
VPP
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44 RP
43 W
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
33 BYTE
32 VSS
31 DQ15/A –1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
PIN NOMENCLATURE
A0 – A16 Address Inputs
BYTE
Byte Enable
DQ0 – DQ14 Data In / Out
DQ15/A –1 Data In / Out (word-wide mode),
Low-Order Address (byte-wide mode)
E Chip Enable
G Output Enable
NC No Internal Connection
RP Reset / Deep Power-Down
VCC
VPP
VSS
W
5-V Power Supply
12-V Power Supply for Program / Erase
Ground
Write Enable
description
The TMS28F200BZx is a 262 144 by 8-bit / 131 072 by 16-bit (2 097 152-bit), boot-block flash memory that can
be electrically block-erased and reprogrammed. The TMS28F200BZx is organized in a blocked architecture
consisting of one 16K-byte protected boot block, two 8K-byte parameter blocks, one 96K-byte main block, and
one 128K-byte main block. The device can be ordered with either a top or bottom boot-block configuration.
Operation as a 256K-by 8-bit or a 128K-by16-bit organization is user-definable.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1

                    
                    






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