TMS28F400BZB

D Organization . . . 524 288 by 8 Bits 262 144 by 16 Bits D Array-Blocking Architecture − Two 8K-Byte Parameter Blocks − One 96K-Byte Main Block − Three 128K-Byte Main Blocks − One 16K-Byte Protected Boot Block − Top or Bottom Boot Locations D All Inputs / Outputs TTL Compatible D Maximum Access/Minimum Cycle Time VCC ± 10% ’28F400BZx80 80 ns ’28F400BZx90 90 ns (x = top (T) or bottom (B) boot-block configuration ordered) D 10 000 Program/Erase-Cycles D Two Temperature Ranges − Commercial . . . 0°C to 70°C − Extended . . . − 40°C to 85°C D Low Power Dissipation ( VCC = 5.5 V ) − Active Write . . . 330 mW ( Byte Write) − Active Read . . . 330 mW ( Byte Read) − Active Write . . . 358 mW ( Word Write) − Active Read . . . 330 mW ( Word Read) − Block Erase . . . 165 mW − Standby . . . 0.55 mW (CMOS-Input Levels) − Deep Power-Down Mode . . . 0.0066 mW D Fully Automated On-Chip Erase and Word / Byte-Program Operations D Write Protection for Boot Block D Industry Standard Command State Machine (CSM) − Erase Suspend/Resume − Algorithm-Selection Identifier TMS28F400BZT, TMS28F400BZB 524288 BY 8ĆBIT/262144 BY 16ĆBIT BOOTĆBLOCK FLASH MEMORIES SMJS400E − JUNE 1994 − REVISED JANUARY 1998 DBJ PACKAGE ( TOP VIEW ) VPP NC A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 RP 43 W 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 34 A16 33 BYTE 32 VSS 31 DQ15/A −1 30 DQ7 29 DQ14 28 DQ6 27 DQ13 26 DQ5 25 DQ12...