TMS29F002RT Datasheet: FLASH MEMORIES





TMS29F002RT Datasheet PDF

Part Number TMS29F002RT
Description FLASH MEMORIES
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS29F002RT Datasheet PDF

Features: D Single Power Supply Supports 5-V "10% Read/Write Operation D Organization : . . . 262 144 by 8 Bits D Array-Blocking Architecture − One 16K-Byte Boot Sec tor − Two 8K-Byte Parameter Sectors One 32K-Byte Sector − Three 64K-By te Sectors − Any Combination of Secto rs Can Be Erased. Support Full-Chip Era se − Any Combination of Sectors Can B e Marked as Read-Only D Boot-Code Secto r Architecture − T = Top Sector − B = Bottom Sector D Sector Protection Hardware Protection Method That Disab les Any Combination of Sectors From Wri te or Erase Operations Using Standard P rogramming Equipment D Embedded Program /Erase Algorithms − Automatically Pre -Programs and Erases Any Sector − Aut omatically Programs and Verifies the Pr ogram Data at Specified Address D JEDEC Standards − Compatible With JEDEC By te Pinouts − Compatible With JEDEC EE PROM Command Set D Fully Automated On-C hip Erase and Program Operations D 100 000 Program/Erase Cycles D Low Power Dissipation D Low Current Consumption − 25-mA Typica.

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TMS29F002RT datasheet
D Single Power Supply Supports 5-V "10%
Read/Write Operation
D Organization : . . . 262 144 by 8 Bits
D Array-Blocking Architecture
− One 16K-Byte Boot Sector
− Two 8K-Byte Parameter Sectors
− One 32K-Byte Sector
− Three 64K-Byte Sectors
− Any Combination of Sectors Can Be
Erased. Support Full-Chip Erase
− Any Combination of Sectors Can Be
Marked as Read-Only
D Boot-Code Sector Architecture
− T = Top Sector
− B = Bottom Sector
D Sector Protection
− Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
D Embedded Program/Erase Algorithms
− Automatically Pre-Programs and Erases
Any Sector
− Automatically Programs and Verifies the
Program Data at Specified Address
D JEDEC Standards
− Compatible With JEDEC Byte Pinouts
− Compatible With JEDEC EEPROM
Command Set
D Fully Automated On-Chip Erase and
Program Operations
D 100 000 Program/Erase Cycles
D Low Power Dissipation
D Low Current Consumption
− 25-mA Typical Active Read
− 30-mA Typical Program/Erase Current
− Less Than 100-µA Standby Current
D All Inputs/Outputs TTL-Compatible
D Erase Suspend/Resume
− Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
D Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
TMS29F002RT, TMS29F002RB
262ā144 BY 8ĆBIT
FLASH MEMORIES
SMJS849B − MARCH 1997 − REVISED JUNE 1998
FM PACKAGE
32-PIN PLCC
(TOP VIEW)
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 DQ7
14 15 16 17 18 19 20
A[0:17]
DQ[0:7]
CE
OE
RESET
VCC
VSS
WE
PIN NOMENCLATURE
Address Inputs
Data In / Data out
Chip Enable
Output Enable
Reset / Deep Power Down
Power Supply
Ground
Write Enable
D 32-Pin Plastic Leaded Chip Carrier (PLCC)
(FM Suffix)
D Detection Of Program/Erase Operation
− Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
D High-Speed Data Access at 5-V VCC"10%
− 90 ns Commercial . . . 0°C to 70°C
− 100 ns Extended . . . −40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
1

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