TMS29LF008B Datasheet: FLASH MEMORIES





TMS29LF008B Datasheet PDF

Part Number TMS29LF008B
Description FLASH MEMORIES
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS29LF008B Datasheet PDF

Features: D Single Power Supply Supports 2.7-V and 3.6-V Read/Write Operation D Organizat ion . . . 1 048576 By 8 Bits D Array Bl ocking Architecture – One 16K-Byte Bo ot Sector – Two 8K-Byte Parameter Sec tors – One 32K-Byte Sector – Fiftee n 64K-Byte Sectors – Any Combination of Sectors Can Be Erased. Supports Full -Chip Erase – Any Combination of Sect ors Can Be Marked as Read-Only D Boot-C ode Sector Architecture – T = Top Sec tor – B = Bottom Sector D Sector Prot ection – Hardware Protection Method T hat Disables Any Combination of Sectors From Write or Erase Operations Using S tandard Programming Equipment D Embedde d Program/Erase Algorithms – Automati cally Pre-Programs and Erases Any Secto r – Automatically Programs and Verifi es the Program Data at Specified Addres s D JEDEC Standards – Compatible With JEDEC Byte Pinouts – Compatible With JEDEC EEPROM Command Set D Fully Autom ated On-Chip Erase and Program Operatio ns D 100 000 Program/Erase Cycles D Low Power Dissipation D Low Current Consumption – 20-.

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TMS29LF008B datasheet
D Single Power Supply Supports 2.7-V and
3.6-V Read/Write Operation
D Organization . . . 1 048576 By 8 Bits
D Array Blocking Architecture
– One 16K-Byte Boot Sector
– Two 8K-Byte Parameter Sectors
– One 32K-Byte Sector
– Fifteen 64K-Byte Sectors
– Any Combination of Sectors Can Be
Erased. Supports Full-Chip Erase
– Any Combination of Sectors Can Be
Marked as Read-Only
D Boot-Code Sector Architecture
– T = Top Sector
– B = Bottom Sector
D Sector Protection
– Hardware Protection Method That
Disables Any Combination of Sectors
From Write or Erase Operations Using
Standard Programming Equipment
D Embedded Program/Erase Algorithms
– Automatically Pre-Programs and Erases
Any Sector
– Automatically Programs and Verifies the
Program Data at Specified Address
D JEDEC Standards
– Compatible With JEDEC Byte Pinouts
– Compatible With JEDEC EEPROM
Command Set
D Fully Automated On-Chip Erase and
Program Operations
D 100 000 Program/Erase Cycles
D Low Power Dissipation
D Low Current Consumption
– 20-mA Typical Active Read for Byte Mode
– 30-mA Typical Program / Erase Current
– Less Than 60-µA Standby Current
– 5 µA in Deep Power-Down Mode
TMS29LF008T, TMS29LF008B
1048576 BY 8-BIT
FLASH MEMORIES
SMJS846A – MAY 1997 – REVISED NOVEMBER 1997
D All Inputs/Outputs TTL-Compatible
D Erase Suspend/Resume
– Supports Reading Data From, or
Programming Data to, a Sector Not
Being Erased
D Hardware-Reset Pin Initializes the
Internal-State Machine to the Read
Operation
D 40-Pin Thin Small-Outline Package (TSOP)
(DCD Suffix)
D Detection Of Program/Erase Operation
– Data Polling and Toggle Bit Feature of
Program/Erase Cycle Completion
– Hardware Method for Detection of
Program/Erase Cycle Completion
Through Ready/Busy (RY/BY) Output Pin
"D High-Speed Data Access at 3.3-V VCC 10%
at Three Temperature Ranges
– 90 ns Commercial . . . 0°C to 70°C
– 100 ns Extended . . . –40°C to 85°C
– 120 ns Automotive . . . –40°C to 125°C
A[0 :19]
DQ[0 : 7]
CE
OE
NC
RESET
RY / BY
VCC
VSS
WE
PIN NOMENCLATURE
Address Inputs
Data In / Data out
Chip Enable
Output Enable
No Internal Connection
Reset / Deep Power Down
Ready / Busy Output
Power Supply
Ground
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright © 1997 Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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