TMS320C30 Datasheet: DIGITAL SIGNAL PROCESSORS





TMS320C30 DIGITAL SIGNAL PROCESSORS Datasheet

Part Number TMS320C30
Description DIGITAL SIGNAL PROCESSORS
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS320C30 Datasheet PDF

Features: TMS320C30 DIGITAL SIGNAL PROCESSOR D Hi gh-Performance Floating-Point Digital S ignal Processor (DSP) โ€“ TMS320C30-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS โ€“ TMS320C30- 40 (5 V) 50-ns Instruction Cycle Time 2 20 MOPS, 40 MFLOPS, 20 MIPS โ€“ TMS320C 30-33 (5 V) 60-ns Instruction Cycle Tim e 183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS โ€ “ TMS320C30-27 (5 V) 74-ns Instruction Cycle Time 148.5 MOPS, 27 MFLOPS, 13.5 MIPS D 32-Bit High-Performance CPU D 16 - / 32-Bit Integer and 32- / 40-Bit Flo ating-Point Operations D 32-Bit Instruc tion Word, 24-Bit Addresses D Two 1K ร— 32-Bit Single-Cycle Dual-Access On-Chi p RAM Blocks D One 4K ร— 32-Bit Single- Cycle Dual-Access On-Chip ROM Block D O n-Chip Memory-Mapped Peripherals: โ€“ T wo Serial Ports โ€“ Two 32-Bit Timers โ €“ One-Channel Direct Memory Access (DM A) Coprocessor for Concurrent I/O and C PU Operation description SPRS032A โ€“ APRIL 1996 โ€“ REVISED JUNE 1997 D Two 32-Bit External Ports D 24- and 13-Bit Addresses D 0.7-ยตm Enhanced Performance Impl.

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TMS320C30
DIGITAL SIGNAL PROCESSOR
D High-Performance Floating-Point Digital
Signal Processor (DSP)
โ€“ TMS320C30-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
โ€“ TMS320C30-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
โ€“ TMS320C30-33 (5 V)
60-ns Instruction Cycle Time
183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS
โ€“ TMS320C30-27 (5 V)
74-ns Instruction Cycle Time
148.5 MOPS, 27 MFLOPS, 13.5 MIPS
D 32-Bit High-Performance CPU
D 16- / 32-Bit Integer and 32- / 40-Bit
Floating-Point Operations
D 32-Bit Instruction Word, 24-Bit Addresses
D Two 1K ร— 32-Bit Single-Cycle Dual-Access
On-Chip RAM Blocks
D One 4K ร— 32-Bit Single-Cycle Dual-Access
On-Chip ROM Block
D On-Chip Memory-Mapped Peripherals:
โ€“ Two Serial Ports
โ€“ Two 32-Bit Timers
โ€“ One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
description
SPRS032A โ€“ APRIL 1996 โ€“ REVISED JUNE 1997
D Two 32-Bit External Ports
D 24- and 13-Bit Addresses
D 0.7-ยตm Enhanced Performance Implanted
CMOS (EPICโ„ข) Technology
D 208-Pin Plastic Quad Flat Package
( PPM Suffix )
D 181-Pin Grid Array Ceramic Package
(GEL Suffix)
D Eight Extended-Precision Registers
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
D Two- and Three-Operand Instructions
D Parallel Arithmetic and Logic Unit (ALU)
and Multiplier Execution in a Single Cycle
D Block-Repeat Capability
D Zero-Overhead Loops With Single-Cycle
Branches
D Conditional Calls and Returns
D Interlocked Instructions for
Multiprocessing Support
D Two Sets of Memory Strobes (STRB and
MSTRB) and One I / O Strobe (IOSTRB)
D Separate Bus-Control Registers for Each
Strobe-Control Wait-State Generation
The TMS320C30 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TIโ„ข).
The TMS320C30 is a 32-bit floating-point processor manufactured in 0.7-ยตm triple-level-metal CMOS
technology.
The TMS320C30โ€™s internal busing and special DSP instruction set have the speed and flexibility to execute up
to 50 MFLOPS (million floating-point operations per second). The TMS320C30 optimizes speed by
implementing functions in hardware that other processors implement through software or microcode. This
hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I / O, and a short machine-cycle time.
High performance and ease of use are results of these features.
General-purpose applications are enhanced greatly by the large address space, multiprocessor interface,
internally and externally generated wait states, two external interface ports, two timers, serial ports, and multiple
interrupt structure. The TMS320C30 supports a wide variety of system applications from host processor to
dedicated coprocessor.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright ยฉ 1997, Texas Instruments Incorporated
โ€ขPOST OFFICE BOX 1443 HOUSTON, TEXAS 77251โ€“1443
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