TMS320C30

TMS320C30 DIGITAL SIGNAL PROCESSOR D High-Performance Floating-Point Digital Signal Processor (DSP) – TMS320C30-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS – TMS320C30-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – TMS320C30-33 (5 V) 60-ns Instruction Cycle Time 183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS – TMS320C30-27 (5 V) 74-ns Instruction Cycle Time 148.5 MOPS, 27 MFLOPS, 13.5 MIPS D 32-Bit High-Performance CPU D 16- / 32-Bit Integer and 32- / 40-Bit Floating-Point Operations D 32-Bit Instruction Word, 24-Bit Addresses D Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks D One 4K × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block D On-Chip Memory-Mapped Peripherals: – Two Serial Ports – Two 32-Bit Timers – One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation description SPRS032A – APRIL 1996 – REVISED JUNE 1997 D Two 32-Bit External Ports D 24- and 13-Bit Addresses D 0.7-µm Enhanced Performance Implanted CMOS (EPIC™) Technology D 208-Pin Plastic Quad Flat Package ( PPM Suffix ) D 181-Pin Grid Array Ceramic Package (GEL Suffix) D Eight Extended-Precision Registers D Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) D Two- and Three-Operand Instructions D Parallel Arithmetic and Logic Unit (ALU) and Multiplier Execution in a Single Cycle D Block-Repeat Capability D Zero-Overhead Loops With Single-Cycle Branches D Conditional Calls and R...