TMS320C511A

D Powerful 16-Bit TMS320C511A CPU D 20-, 20.8-, and 21.7-ns Single-Cycle Instruction Execution Time With 5-V Operation D Single-Cycle 16 × 16-Bit Multiply/Add D 128K Words of Total Data/Program Space D 6 × 4K × 16-Bit Single-Access On-Chip Program ROM D 1K × 16-Bit Dual-Access On-Chip Program/Data RAM D Full-Duplex Synchronous Serial Port for Code / Decode (CODEC) Interface D Hardware or Software Wait-State Generation Capability D Repeat Instructions for Efficient Use of Program Space D Multiply-by-Two and Divide-by-Two Clocking Options TMS320C511A DIGITAL SIGNAL PROCESSOR SPRS053 – FEBRUARY 1997 D Block Moves for Data/Program Management D On-Chip Scan-Based Emulation Logic D 100-Pin Quad Flat Package (PJ Suffix) and 100-Pin Thin Quad Flat Package (PZ Suffix) D Low-Power Dissipation and Power-Down Modes: – 47 mA (2.35 mA/MIPS) at 5 V, 40-MHz Clock (Average) – 3 mA at 5 V, 40-MHz Clock (Typical IDLE2) – 5 µA at 5 V, Clocks Off (Typical STANDBY) D High-Performance Static CMOS Technology D Databus Keepers description The TMS320C511A is a member of the ’C5x generation of the Texas Instruments (TI™) TMS320 digital signal processors (DSPs). This device is fabricated with static CMOS integrated circuit technology, and its architectural design is based on that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the...