TMS320C6713 Datasheet: Floating-Point Digital Signal Processor





TMS320C6713 Floating-Point Digital Signal Processor Datasheet

Part Number TMS320C6713
Description Floating-Point Digital Signal Processor
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS320C6713 Datasheet PDF

Features: TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS186I โˆ ’ DECEMBER 2001 โˆ’ REVISED MAY 2004 D Highest-Performance Floating-Point Dig ital Signal Processors (DSPs): C6713/C6 713B โˆ’ Eight 32-Bit Instructions/Cycl e โˆ’ 32/64-Bit Data Word โˆ’ 300-, 225 -, 200-MHz (GDP), and 200-, 167-MHz (PY P) Clock Rates โˆ’ 3.3-, 4.4-, 5-, 6-In struction Cycle Times โˆ’ 2400/1800, 18 00 /1350 , 1600 /1200 , and 1336 /1000 MIPS /MFLOPS โˆ’ Rich Peripheral Set, O ptimized for Audio โˆ’ Highly Optimized C/C++ Compiler D Advanced Very Long In struction Word (VLIW) TMS320C67x๏ฃช DSP Core โˆ’ Eight Independent Functional Units: โˆ’ Two ALUs (Fixed-Point) โˆ’ F our ALUs (Floating- and Fixed-Point) โˆ ’ Two Multipliers (Floating- and Fixed- Point) โˆ’ Load-Store Architecture With 32 32-Bit General-Purpose Registers โˆ ’ Instruction Packing Reduces Code Size โˆ’ All Instructions Conditional D Ins truction Set Features โˆ’ Native Instru ctions for IEEE 754 โˆ’ Single- and Double-Precision โˆ’ Byte-Addressable (8-, 16-, 32-Bit Data) โˆ’ 8-Bi.

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TMS320C6713, TMS320C6713B
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS186I โˆ’ DECEMBER 2001 โˆ’ REVISED MAY 2004
D Highest-Performance Floating-Point Digital
Signal Processors (DSPs): C6713/C6713B
โˆ’ Eight 32-Bit Instructions/Cycle
โˆ’ 32/64-Bit Data Word
โˆ’ 300-, 225-, 200-MHz (GDP), and 200-,
167-MHz (PYP) Clock Rates
โˆ’ 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
โˆ’ 2400/1800, 1800 /1350 , 1600 /1200 , and
1336 /1000 MIPS /MFLOPS
โˆ’ Rich Peripheral Set, Optimized for Audio
โˆ’ Highly Optimized C/C++ Compiler
D Advanced Very Long Instruction Word
(VLIW) TMS320C67x๏ฃช DSP Core
โˆ’ Eight Independent Functional Units:
โˆ’ Two ALUs (Fixed-Point)
โˆ’ Four ALUs (Floating- and Fixed-Point)
โˆ’ Two Multipliers (Floating- and
Fixed-Point)
โˆ’ Load-Store Architecture With 32 32-Bit
General-Purpose Registers
โˆ’ Instruction Packing Reduces Code Size
โˆ’ All Instructions Conditional
D Instruction Set Features
โˆ’ Native Instructions for IEEE 754
โˆ’ Single- and Double-Precision
โˆ’ Byte-Addressable (8-, 16-, 32-Bit Data)
โˆ’ 8-Bit Overflow Protection
โˆ’ Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
D L1/L2 Memory Architecture
โˆ’ 4K-Byte L1P Program Cache
(Direct-Mapped)
โˆ’ 4K-Byte L1D Data Cache (2-Way)
โˆ’ 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
D Device Configuration
โˆ’ Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
โˆ’ Endianness: Little Endian, Big Endian
D 32-Bit External Memory Interface (EMIF)
โˆ’ Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
โˆ’ 512M-Byte Total Addressable External
Memory Space
D 16-Bit Host-Port Interface (HPI)
D Two Multichannel Audio Serial Ports
(McASPs)
โˆ’ Two Independent Clock Zones Each
(1 TX and 1 RX)
โˆ’ Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
โˆ’ Each Clock Zone Includes:
โˆ’ Programmable Clock Generator
โˆ’ Programmable Frame Sync Generator
โˆ’ TDM Streams From 2-32 Time Slots
โˆ’ Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
โˆ’ Data Formatter for Bit Manipulation
โˆ’ Wide Variety of I2S and Similar Bit
Stream Formats
โˆ’ Integrated Digital Audio Interface
Transmitter (DIT) Supports:
โˆ’ S/PDIF, IEC60958-1, AES-3, CP-430
Formats
โˆ’ Up to 16 transmit pins
โˆ’ Enhanced Channel Status/User Data
โˆ’ Extensive Error Checking and Recovery
D Two Inter-Integrated Circuit Bus (I2C Bus๏ฃช)
Multi-Master and Slave Interfaces
D Two Multichannel Buffered Serial Ports:
โˆ’ Serial-Peripheral-Interface (SPI)
โˆ’ High-Speed TDM Interface
โˆ’ AC97 Interface
D Two 32-Bit General-Purpose Timers
D Dedicated GPIO Module With 16 pins
(External Interrupt Capable)
D Flexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
D IEEE-1149.1 (JTAGโ€ )
Boundary-Scan-Compatible
D Package Options:
โˆ’ 208-Pin PowerPAD๏ฃช Plastic (Low-Profile)
Quad Flatpack (PYP)
โˆ’ 272-Ball, Ball Grid Array Package (GDP)
D 0.13-ยตm/6-Level Copper Metal Process
โˆ’ CMOS Technology
D Enhanced Direct-Memory-Access (EDMA)
D 3.3-V I/Os, 1.2โ€ก-V Internal (GDP & PYP)
Controller (16 Independent Channels)
D 3.3-V I/Os, 1.4-V Internal (GDP) (300 MHz
only)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I2C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
โ€  IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
โ€ก These values are compatible with existing 1.26V designs.
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright ๏ฃฉ 2004, Texas Instruments Incorporated
โ€ขPOST OFFICE BOX 1443 HOUSTON, TEXAS 77251โˆ’1443
1

                    
                    






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