DatasheetsPDF.com

TMS320C50 Dataheets PDF



Part Number TMS320C50
Manufacturers Texas Instruments
Logo Texas Instruments
Description DIGITAL SIGNAL PROCESSORS
Datasheet TMS320C50 DatasheetTMS320C50 Datasheet (PDF)

D Powerful 16-Bit TMS320C5x CPU D 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation D 25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation D Single-Cycle 16 × 16-Bit Multiply/Add D 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) D 2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access On-Chip Program ROM D 1K, 3K, 6K, 9K × 16-Bit Single-Access On-Chip Program / Data RAM (SARAM) D 1K Dual-Acces.

  TMS320C50   TMS320C50


Document
D Powerful 16-Bit TMS320C5x CPU D 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation D 25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation D Single-Cycle 16 × 16-Bit Multiply/Add D 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) D 2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access On-Chip Program ROM D 1K, 3K, 6K, 9K × 16-Bit Single-Access On-Chip Program / Data RAM (SARAM) D 1K Dual-Access On-Chip Program / Data RAM (DARAM) D Full-Duplex Synchronous Serial Port for Coder/Decoder Interface D Time-Division-Multiplexed (TDM) Serial Port D Hardware or Software Wait-State Generation Capability D On-Chip Timer for Control Operations D Repeat Instructions for Efficient Use of Program Space D Buffered Serial Port D Host Port Interface TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 D Multiple Phase-Locked Loop (PLL) Clocking Options (×1, ×2, ×3, ×4, ×5, ×9 Depending on Device) D Block Moves for Data/Program Management D On-Chip Scan-Based Emulation Logic D Boundary Scan D Five Packaging Options – 100-Pin Quad Flat Package (PJ Suffix) – 100-Pin Thin Quad Flat Package (PZ Suffix) – 128-Pin Thin Quad Flat Package (PBK Suffix) – 132-Pin Quad Flat Package (PQ Suffix) – 144-Pin Thin Quad Flat Package (PGE Suffix) D Low Power Dissipation and Power-Down Modes: – 47 mA (2.35 mA / MIP) at 5 V, 40-MHz Clock (Average) – 23 mA (1.15 mA / MIP) at 3 V, 40-MHz Clock (Average) – 10 mA at 5 V, 40-MHz Clock (IDLE1 Mode) – 3 mA at 5 V, 40-MHz Clock (IDLE2 Mode) – 5 µA at 5 V, Clocks Off (IDLE2 Mode) D High-Performance Static CMOS Technology D IEEE Standard 1149.1† Test-Access Port (JTAG) description The TMS320C5x generation of the Texas Instruments (TI™) TMS320 digital signal processors (DSPs) is fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of the ’C5x‡ devices. They execute up to 50 million instructions per second (MIPS). The ’C5x devices offer these advantages: D Enhanced TMS320 architectural design for increased performance and versatility D Modular architectural design for fast development of spin-off devices D Advanced integrated-circuit processing technology for increased performance D Upward-compatible source code (source code for ’C1x and ’C2x DSPs is upward compatible with ’C5x DSPs.) D Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation D New static-design techniques for minimizing power consumption and maximizing radiation tolerance Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments Incorporated. † IEEE Standard 1149.1–1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture ‡ References to ’C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated •POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 1 TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 description (continued) Table 1 provides a comparison of the devices in the ’C5x generation. It shows the capacity of on-chip RAM and ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of package with total pin count. Table 1. Characteristics of the ’C5x Processors TMS320 DEVICES ON-CHIP MEMORY (16-BIT WORDS) DARAM SARAM ROM DATA DATA + PROG DATA + PROG PROG I/O PORTS SERIAL PARALLEL† TMS320C50 544 512 9K 2K§ 2 64K TMS320LC50 544 512 9K 2K§ 2 64K TMS320C51 544 512 1K 8K§ 2 64K TMS320LC51 544 512 1K 8K§ 2 64K TMS320C52 544 512 – 4K§ 1¶ 64K TMS320LC52 544 512 – 4K§ 1¶ 64K TMS320C53 544 512 3K 16K§ 2 64K TMS320LC53 544 512 3K 16K§ 2 64K TMS320C53S 544 512 3K 16K§ 2¶ 64K TMS320LC53S 544 512 3K 16K§ 2¶ 64K TMS320LC56 544 512 6K 32K 2# 64K TMS320LC57 544 512 6K 32K 2 # 64K + HPI || TMS320C57S 544 512 6K 2K§ 2 # 64K + HPI || TMS320LC57S 544 512 6K 2K§ 2# † Sixteen of the 64K parallel I/O ports are memory mapped. ‡ QFP = Quad flatpack § ROM boot loader available ¶ TDM serial port not availabl.


TMS320F241 TMS320C50 TMS320LC50


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)