TMS320C57S

D Powerful 16-Bit TMS320C5x CPU D 20-, 25-, 35-, and 50-ns Single-Cycle Instruction Execution Time for 5-V Operation D 25-, 40-, and 50-ns Single-Cycle Instruction Execution Time for 3-V Operation D Single-Cycle 16 × 16-Bit Multiply/Add D 224K × 16-Bit Maximum Addressable External Memory Space (64K Program, 64K Data, 64K I/O, and 32K Global) D 2K, 4K, 8K, 16K, 32K × 16-Bit Single-Access On-Chip Program ROM D 1K, 3K, 6K, 9K × 16-Bit Single-Access On-Chip Program / Data RAM (SARAM) D 1K Dual-Access On-Chip Program / Data RAM (DARAM) D Full-Duplex Synchronous Serial Port for Coder/Decoder Interface D Time-Division-Multiplexed (TDM) Serial Port D Hardware or Software Wait-State Generation Capability D On-Chip Timer for Control Operations D Repeat Instructions for Efficient Use of Program Space D Buffered Serial Port D Host Port Interface TMS320C5x, TMS320LC5x DIGITAL SIGNAL PROCESSORS SPRS030A – APRIL 1995 – REVISED APRIL 1996 D Multiple Phase-Locked Loop (PLL) Clocking Options (×1, ×2, ×3, ×4, ×5, ×9 Depending on Device) D Block Moves for Data/Program Management D On-Chip Scan-Based Emulation Logic D Boundary Scan D Five Packaging Options – 100-Pin Quad Flat Package (PJ Suffix) – 100-Pin Thin Quad Flat Package (PZ Suffix) – 128-Pin Thin Quad Flat Package (PBK Suffix) – 132-Pin Quad Flat Package (PQ Suffix) – 144-Pin Thin Quad Flat Package (PGE Suffix) D Low Power Dissipation and Power-Down Modes: – 47 mA (2.35 mA / MIP) at 5 V, 40-MHz Clock (Average) – 23 mA (1.15 mA / MIP) at ...