TMS320C31

TMS320C31, TMS320LC31 DIGITAL SIGNAL PROCESSORS D High-Performance Floating-Point Digital Signal Processor (DSP): – TMS320C31-80 (5 V) 25-ns Instruction Cycle Time 440 MOPS, 80 MFLOPS, 40 MIPS – TMS320C31-60 (5 V) 33-ns Instruction Cycle Time 330 MOPS, 60 MFLOPS, 30 MIPS – TMS320C31-50 (5 V) 40-ns Instruction Cycle Time 275 MOPS, 50 MFLOPS, 25 MIPS – TMS320C31-40 (5 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – TMS320LC31-40 (3.3 V) 50-ns Instruction Cycle Time 220 MOPS, 40 MFLOPS, 20 MIPS – TMS320LC31-33 (3.3 V) 60-ns Instruction Cycle Time 183.7 MOPS, 33.3 MFLOPS, 16.7 MIPS D 32-Bit High-Performance CPU D 16- / 32-Bit Integer and 32- / 40-Bit Floating-Point Operations D 32-Bit Instruction Word, 24-Bit Addresses D Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks D Boot-Program Loader description SPRS035B – MARCH 1996 – REVISED JANUARY 1999 D On-Chip Memory-Mapped Peripherals: – One Serial Port – Two 32-Bit Timers – One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation D Fabricated Using 0.6 µm Enhanced Performance Implanted CMOS (EPIC™) Technology by Texas Instruments (TI™) D 132-Pin Plastic Quad Flat Package ( PQ Suffix ) D Eight Extended-Precision Registers D Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) D Two Low-Power Modes D Two- and Three-Operand Instructions D Parallel Arithmetic / Logic Unit (ALU) and Multiplier Execution in a Single Cycle D Blo...