TMS320TCI100 Datasheet: DIGITAL SIGNAL PROCESSOR





TMS320TCI100 DIGITAL SIGNAL PROCESSOR Datasheet

Part Number TMS320TCI100
Description DIGITAL SIGNAL PROCESSOR
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS320TCI100 Datasheet PDF

Features: TMS320TCI100 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS218I − MAY 2003 − R EVISED APRIL 2009 D Highest-Performanc e Fixed-Point Digital − 8M-Bit (1024 K-Byte) L2 Unified Mapped Signal Proce ssors (DSPs) RAM/Cache (Flexible Alloc ation) − 1.67-, 1.39-ns Instruction Cycle Time − 600-, 720-MHz Clock Rate − Eight 32-Bit Instructions/Cycle Twenty-Eight Operations/Cycle − 480 0, 5760 MIPS − Fully Software-Compati ble With C62x − TCI100/C6416 Pin-C ompatible − Extended Temperature Devi ces Available D VelociTI.2 Extension s to VelociTI Advanced Very-Long-Ins truction-Word (VLIW) TMS320C64x DSP Core − Eight Highly Independent Funct ional Units With VelociTI.2 Extensio ns: − Six ALUs (32-/40-Bit), Each Sup ports Single 32-Bit, Dual 16-Bit, or Qu ad 8-Bit Arithmetic per Clock Cycle − Two Multipliers Support Four 16 x 16-B it Multiplies (32-Bit Results) per Cloc k Cycle or Eight 8 x 8-Bit Multiplies ( 16-Bit Results) per Clock Cycle − Non-Aligned Load-Store Architecture − 64 32-Bit General-Purpose Regi.

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TMS320TCI100
FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS218I − MAY 2003 − REVISED APRIL 2009
D Highest-Performance Fixed-Point Digital
− 8M-Bit (1024K-Byte) L2 Unified Mapped
Signal Processors (DSPs)
RAM/Cache (Flexible Allocation)
− 1.67-, 1.39-ns Instruction Cycle Time
− 600-, 720-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− Twenty-Eight Operations/Cycle
− 4800, 5760 MIPS
− Fully Software-Compatible With C62x
− TCI100/C6416 Pin-Compatible
− Extended Temperature Devices Available
D VelociTI.2Extensions to VelociTI
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64xDSP Core
− Eight Highly Independent Functional
Units With VelociTI.2Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
D Two External Memory Interfaces (EMIFs)
− One 64-Bit (EMIFA), One 16-Bit (EMIFB)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
− 1280M-Byte Total Addressable External
Memory Space
D Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
D Host-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
D 32-Bit/33-MHz, 3.3-V PCI Master/Slave
Interface Conforms to PCI Specification 2.2
− Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP
Program Control
− DSP Interrupt Via PCI I/O Cycle
D Three Multichannel Buffered Serial Ports
− Instruction Packing Reduces Code Size
− Direct Interface to T1/E1, MVIP, SCSA
− All Instructions Conditional
Framers
D Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− Up to 256 Channels Each
− ST-Bus-Switching-, AC97-Compatible
− Serial Peripheral Interface (SPI)
Compatible (Motorola)
D Three 32-Bit General-Purpose Timers
− VelociTI.2Increased Orthogonality
D VCP
D UTOPIA
− UTOPIA Level 2 Slave ATM Controller
− Supports Over 600 7.95-Kbps AMR
− 8-Bit Transmit and Receive Operations
− Programmable Code Parameters
up to 50 MHz per Direction
D TCP
− Supports up to Seven 2-Mbps 3GPP
− User-Defined Cell Format up to 64 Bytes
D Sixteen General-Purpose I/O (GPIO) Pins
(6 Iterations)
− Programmable Turbo Code and
Decoding Parameters
D L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
D Flexible PLL Clock Generator
D IEEE-1149.1 (JTAG)
Boundary-Scan-Compatible
D 532-Pin Ball Grid Array (BGA) Package
(GLZ, ZLZ, CLZ Suffixes), 0.8-mm Ball Pitch
D 0.09-µm/7-Level Cu Metal Process (CMOS)
D 3.3-V I/Os, 1.1-V Internal (600 MHz)
D 3.3-V I/Os, 1.2-V Internal (720 MHz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2009, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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