TMS320TCI6482 Datasheet: DIGITAL SIGNAL PROCESSOR





TMS320TCI6482 DIGITAL SIGNAL PROCESSOR Datasheet

Part Number TMS320TCI6482
Description DIGITAL SIGNAL PROCESSOR
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS320TCI6482 Datasheet PDF

Features: TMS320TCI6482 www.ti.com SPRS246K – APRIL 2005 – REVISED MARCH 2012 TMS3 20TCI6482 Communications Infrastructur e Digital Signal Processor Check for S amples: TMS320TCI6482 1 Features 12 †¢ High-Performance Communications Infra structure DSP (TCI6482) – 1.17-, 1-, and 0.83-ns Instruction Cycle Time – 850-MHz, 1-GHz, and 1.2-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – 9600 MIPS/MMACS (16-Bits) – Commerci al Temperature [0°C to 90°C] – Exte nded Temperature [-40°C to 105°C] • TMS320C64x+™ DSP Core – Dedicated SPLOOP Instruction – Compact Instruct ions (16-Bit) – Instruction Set Enhan cements – Exception Handling • TMS3 20C64x+ Megamodule L1/L2 Memory Archite cture: – 256K-Bit (32K-Byte) L1P Prog ram Cache [Direct Mapped] – 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-As sociative] – 16M-Bit (2048K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allo cation] – 256K-Bit (32K-Byte) L2 ROM – Time Stamp Counter • 2 RSAs for CDMA Processing – Dedicated RAKE, PATH_SEARCH and RACH_SEARCH Instruction.

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TMS320TCI6482
www.ti.com
SPRS246K – APRIL 2005 – REVISED MARCH 2012
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
Check for Samples: TMS320TCI6482
1 Features
12
• High-Performance Communications
Infrastructure DSP (TCI6482)
– 1.17-, 1-, and 0.83-ns Instruction Cycle Time
– 850-MHz, 1-GHz, and 1.2-GHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 9600 MIPS/MMACS (16-Bits)
– Commercial Temperature [0°C to 90°C]
– Extended Temperature [-40°C to 105°C]
• TMS320C64x+™ DSP Core
– Dedicated SPLOOP Instruction
– Compact Instructions (16-Bit)
– Instruction Set Enhancements
– Exception Handling
• TMS320C64x+ Megamodule L1/L2 Memory
Architecture:
– 256K-Bit (32K-Byte) L1P Program Cache
[Direct Mapped]
– 256K-Bit (32K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 16M-Bit (2048K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
– 256K-Bit (32K-Byte) L2 ROM
– Time Stamp Counter
• 2 RSAs for CDMA Processing
– Dedicated RAKE, PATH_SEARCH and
RACH_SEARCH Instructions
– Transmit Processing Capability
• Enhanced Viterbi Decoder Coprocessor (VCP2)
– Supports Over 694 7.95-Kbps AMR
– Programmable Code Parameters
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Supports up to Eight 2-Mbps 3GPP
(6 Iterations)
– Programmable Turbo Code and Decoding
Parameters
• Endianess: Little Endian, Big Endian
• 64-Bit External Memory Interface (EMIFA)
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM) and
Synchronous Memories (SBSRAM, ZBT
SRAM)
– Supports Interface to Standard Sync Devices
and Custom Logic
(FPGA, CPLD, ASICs, etc.)
– 32M-Byte Total Addressable External
Memory Space
• Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
– 1.25-, 2.5-, 3.125-Gbps Link Rates
– Message Passing, DirectIO Support, Error
Mgmt Extensions, Congestion Control
– IEEE 1149.6 Compliant I/Os
• DDR2 Memory Controller
– Interfaces to DDR2-533 SDRAM
– 32-Bit/16-Bit, 533-MHz (data rate) Bus
– 512M-Byte Total Addressable External
Memory Space
• EDMA3 Controller (64 Independent Channels)
• 32-/16-Bit Host-Port Interface (HPI)
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Local Bus Specification (v2.3)
• One Inter-Integrated Circuit (I2C) Bus
• Two McBSPs
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Supports Multiple Media Independent
Interfaces (MII, GMII, RMII, and RGMII)
– 8 Independent Transmit (TX) and
8 Independent Receive (RX) Channels
• Two 64-Bit General-Purpose Timers,
Configurable as Four 32-Bit Timers
• UTOPIA
– UTOPIA Level 2 Slave ATM Controller
– 8-Bit Transmit and Receive Operations up to
50 MHz per Direction
– User-Defined Cell Format up to 64 Bytes
• VLYNQ™ Port
– Full Duplex Serial Bus
– Up to 4-Bit Transmit, 4-Bit Receive
– Up to 125-MHz Operation
• 16 General-Purpose I/O (GPIO) Pins
• System PLL and PLL Controller
• Secondary PLL and PLL Controller, Dedicated
to EMAC and DDR2 Memory Controller
• Advanced Event Triggering (AET) Compatible
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2005–2012, Texas Instruments Incorporated

                    
                    






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