TMS320TCI6482

TMS320TCI6482 www.ti.com SPRS246K – APRIL 2005 – REVISED MARCH 2012 TMS320TCI6482 Communications Infrastructure Digital Signal Processor Check for Samples: TMS320TCI6482 1 Features 12 High-Performance Communications Infrastructure DSP (TCI6482) – 1.17-, 1-, and 0.83-ns Instruction Cycle Time – 850-MHz, 1-GHz, and 1.2-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – 9600 MIPS/MMACS (16-Bits) – Commercial Temperature [0°C to 90°C] – Extended Temperature [-40°C to 105°C] TMS320C64x+™ DSP Core – Dedicated SPLOOP Instruction – Compact Instructions (16-Bit) – Instruction Set Enhancements – Exception Handling TMS320C64x+ Megamodule L1/L2 Memory Architecture: – 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped] – 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative] – 16M-Bit (2048K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation] – 256K-Bit (32K-Byte) L2 ROM – Time Stamp Counter 2 RSAs for CDMA Processing – Dedicated RAKE, PATH_SEARCH and RACH_SEARCH Instructions – Transmit Processing Capability Enhanced Viterbi Decoder Coprocessor (VCP2) – Supports Over 694 7.95-Kbps AMR – Programmable Code Parameters Enhanced Turbo Decoder Coprocessor (TCP2) – Supports up to Eight 2-Mbps 3GPP (6 Iterations) – Programmable Turbo Code and Decoding Parameters Endianess: Little Endian, Big Endian 64-Bit External Memory Interface (EMIFA) – Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM) – Supports I...