TMS320TCI6488

www.ti.com TMS320TCI6487 TMS320TCI6488 Communications Infrastructure Digital Signal Processor SPRS358F – APRIL 2007 – REVISED AUGUST 2008 1 Features High-Performance Communications Infrastructure DSP (TCI6487/8) – 1-ns Instruction Cycle Time – 1.0-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – Commercial Temperature 0°C to 100°C 3 TMS320C64x+™ DSP Cores – Dedicated SPLOOP Instructions – Compact Instructions (16-Bit) – Exception Handling TMS320C64x+ Megamodule L1/L2 Memory Architecture – 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped] – 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative] – 24 M-Bit (3072 K-Byte) Total L2 Unified Mapped RAM/Cache [Flexible Allocation] Configurable at boot-time to 1 MB/ 1 MB/1 MB or 1.5 MB/1 MB/0.5 MB – 512 K-Bit (64 K-Byte) L3 ROM One Receive Accelerator (RAC) [TCI6488 Only] – Performs Chip-Rate RX Functions – Up to 64 Macro-BTS Users – Up to 160 km cell size Six RSAs for CDMA Processing (2 per core) – Dedicated RAKE, PATH_SEARCH and RACH_SEARCH Instructions – Transmit Processing Capability Enhanced VCP2 – Supports Over 694 7.95-Kbps AMR Enhanced Turbo Decoder Coprocessor (TCP2) – Supports up to Eight 2-Mbps 3 GPP (6 Iterations) Endianness: Little Endian, Big Endian Frame Synchronization Interface – Time Alignment Between Internal Subsystems, External Devices/System – OBSAI RP1 Compliant for Frame Burst Data – Alternate Interfaces for non-RP1 and non-UMTS Systems 16-/32-Bit DDR2-667 Memory Controller...