TMS55175 Datasheet PDF Download, etcTI





(PDF) TMS55175 Datasheet Download

Part Number TMS55175
Description 262144 BY 16-BIT MULTIPORT VIDEO RAM
Manufacture etcTI
Total Page 30 Pages
PDF Download Download TMS55175 Datasheet PDF

Features: TMS55165, TMS55166, TMS55175, TMS55176 2 62144 BY 16-BIT MULTIPORT VIDEO RAM D Organization: DRAM: 262 144 Words × 16 Bits SAM: 256 Words × 16 Bits D Singl e 5.0-V Power Supply (±10%) D Dual-Por t Accessibility – Simultaneous and As ynchronous Access From the DRAM and Ser ial-Address Memory (SAM) Ports D Write- Per-Bit Function for Selective Write to Each I/O of the DRAM Port D Byte Write Function for Selective Write to Lower Byte (DQ0 – DQ7) or Upper Byte (DQ8 DQ15) of the DRAM Port D 4 - Column o r 8 - Column Block - Write Function for Fast Area - Fill Operations D Enhanced Page Mode for Faster Access With Exten ded-Data-Output (EDO) Option for Faster System Cycle Time D CAS-Before-RAS (CB R) and Hidden Refresh Functions D Long Refresh Period – Every 8 ms (Maximum) D Full - Register- Transfer Function T ransfers Data from the DRAM to the Seri al Register performance ranges SMVS463 – DECEMBER 1995 D Split-Register-Tra nsfer Function Transfers Data from the DRAM to One-Half of the Serial Regist.

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TMS55165, TMS55166, TMS55175, TMS55176
262144 BY 16-BIT MULTIPORT VIDEO RAM
D Organization:
DRAM: 262 144 Words × 16 Bits
SAM: 256 Words × 16 Bits
D Single 5.0-V Power Supply (±10%)
D Dual-Port Accessibility – Simultaneous and
Asynchronous Access From the DRAM and
Serial-Address Memory (SAM) Ports
D Write-Per-Bit Function for Selective Write to
Each I/O of the DRAM Port
D Byte Write Function for Selective Write to
Lower Byte (DQ0 – DQ7) or Upper Byte
(DQ8– DQ15) of the DRAM Port
D 4 - Column or 8 - Column Block - Write
Function for Fast Area - Fill Operations
D Enhanced Page Mode for Faster Access
With Extended-Data-Output (EDO) Option
for Faster System Cycle Time
D CAS-Before-RAS (CBR) and Hidden
Refresh Functions
D Long Refresh Period – Every 8 ms
(Maximum)
D Full - Register- Transfer Function Transfers
Data from the DRAM to the Serial Register
performance ranges
SMVS463 – DECEMBER 1995
D Split-Register-Transfer Function Transfers
Data from the DRAM to One-Half of the
Serial Register While the Other Half is
Outputing Data to the SAM Port
D 256 Selectable Serial Register Starting
Points
D Programmable Split-Register Stop Point
D Up to 55-MHz Uninterrupted Serial-Data
Streams
D 3-State Serial Outputs for Easy Multiplexing
of Video Data Streams
D All Inputs/Outputs and Clocks TTL
Compatible
D Compatible With JEDEC Standards
D Designed to Work With the Texas
Instruments (TI) Graphics Family
D Fabricated Using TI’s Enhanced
Performance Implanted CMOS (EPIC)
Process
– 60 Speed
– 70 Speed
ACCESS TIME
ROW ENABLE
tRAC
(MAX)
60 ns
70 ns
ACCESS TIME
SERIAL DATA
tSCA
(MIN)
15 ns
20 ns
DRAM PAGE
CYCLE TIME
tPC
(MIN)
35 ns
40 ns
DRAM EDO
CYCLE TIME
tPC
(MIN)
30 ns
30 ns
SERIAL
CYCLE TIME
tSCC
(MIN)
18 ns
22 ns
OPERATING CURRENT
SERIAL PORT STANDBY
lCC1
(MAX)
180 mA
165 mA
DEVICE
55165
55166
55175
55176
Table 1. Device Option Table
POWER SUPPLY VOLTAGE
5.0 V ± 0.5 V
5.0 V ± 0.5 V
5.0 V ± 0.5 V
5.0 V ± 0.5 V
BLOCK-WRITE CAPABILITY
4 -column
4 -column
8 - column
8 - column
PAGE / EDO OPERATION
Page
EDO
Page
EDO
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1

                    
                    






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