Document
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995 – REVISED NOVEMBER 1995
D Organization . . . 1 048576 × 16 D Single Power Supply (5 V or 3.3 V) D Performance Ranges:
ACCESS ACCESS ACCESS TIME TIME TIME
READ OR WRITE
DGE PACKAGE ( TOP VIEW )
VCC 1 DQ0 2
50 VSS 49 DQ15
DZ PACKAGE ( TOP VIEW )
VCC 1 DQ0 2
42 VSS 41 DQ15
tRAC MAX
tCAC MAX
tAA MAX
CYCLE MIN
’4xx160/P-60 60 ns 15 ns 30 ns
110 ns
’4xx160/P-70 70 ns 18 ns 35 ns
130 ns
’4xx160/P-80 80 ns 20 ns 40 ns
150 ns
D Enhanced Page-Mode Operation With
CAS-Before-RAS ( CBR) Refresh
D Long Refresh Period and Self-Refresh
Option ( TMS4xx160P)
D 3-State Unlatched Output D Low Power Dissipation D High-Reliability Plastic 42-Lead (DZ Suffix)
400-Mil-Wide Surface-Mount (SOJ) Package
and 44/50-Lead (DGE Suffix) Surface-Mount
Thin Small-Outline Package ( TSOP)
D Operating Free-Air Temperature Range
0°C to 70°C
D Fabricated Using the Texas Instruments
Enhanced Performance Implanted CMOS
(EPIC™) Technology
DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7
NC
3 4 5 6 7 8 9 10 11
NC NC
W RAS A11† A10†
A0 A1
15 16 17 18 19 20 21 22
48 DQ14 47 DQ13 46 DQ12 45 VSS 44 DQ11 43 DQ10 42 DQ9 41 DQ8 40 NC
36 NC 35 LCAS 34 UCAS 33 OE 32 A9 31 A8 30 A7 29 A6
DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7
NC NC
W RAS A11† A10†
A0 A1 A2 A3 VCC
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
40 DQ14 39 DQ13 38 DQ12 37 VSS 36 DQ11 35 DQ10 34 DQ9 33 DQ8 32 NC 31 LCAS 30 UCAS 29 OE 28 A9 27 A8 26 A7 25 A6 24 A5 23 A4 22 VSS
AVAILABLE OPTIONS
A2 23 28 A5
DEVICE
POWER SUPPLY
SELF REFRESH, BATTERY
REFRESH CYCLES
A3 24 VCC 25
27 A4 26 VSS
TMS416160
BACKUP 5 V — 4096 in 64 ms
† A10 and A11 are NC for TMS4x8160 and TMS4x8160P.
TMS416160P
5V
Yes 4096 in 128 ms
TMS418160 TMS418160P TMS426160 TMS426160P TMS428160 TMS428160P
5V 5V 3.3 V 3.3 V 3.3 V 3.3 V
— 1024 in 16 ms Yes 1024 in 128 ms — 4096 in 64 ms Yes 4096 in 128 ms — 1024 in 16 ms Yes 1024 in 128 ms
PIN NOMENCLATURE
A0 – A11 DQ0 – DQ15 LCAS UCAS NC
Address Inputs Data In / Data Out Lower Column-Address Strobe Upper Column-Address Strobe No Internal Connection
description
The TMS4xx160 series is a set of high-speed, 16 777 216-bit dynamic random-access memories (DRAMs) organized as 1 048 576 words of 16
OE
RAS
VCC VSS W
Output Enable
Row-Address Strobe 5-V or 3.3-V Supply‡
Ground
Write Enable
bits each. The TMS4xx160P series is a similar
‡ See Available Options Table.
set of high-speed, low-power, self-refresh,
16 777 216-bit DRAMs organized as 1 048 576 words of 16 bits each. Both sets employ state-of-the-art
enhanced performance implanted CMOS (EPIC™) technology for high performance, reliability, and low power
at low cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
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1
TMS416160, TMS416160P, TMS418160, TMS418160P TMS426160, TMS426160P, TMS428160, TMS428160P 1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995 – REVISED NOVEMBER 1995
description (continued) These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS4xx160 and TMS4xx160P are offered in a 44/50-lead plastic surface-mount TSOP (DGE suffix) and a 42-lead plastic surface-mount SOJ (DZ suffix) package. These packages are characterized for operation from 0°C to 70°C.
•2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
logic symbol†
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995 – REVISED NOVEMBER 1995
A0 17 A1 18 A2 19 A3 20 A4 23 A5 24
25 A6 A7 26 A8 27
28 A9 A10 ‡ 16 A11 ‡ 15 RAS 14 LCAS 31
RAM 1M × 16 20D8/21D0
A
1
0 048
575
20D15/21D7 20D16
20D17 20D18 20D19
C20[ROW] G23/[REFRESH ROW]
24[PWR DWN] C21
G24
& 23C22
31
UCAS 30
W 13 OE 29 DQ0 2 DQ1 3 DQ2 4 DQ3 5 DQ4 7 DQ5 8 DQ6 9 DQ7 10 DQ8 33 DQ9 34 DQ10 35 DQ11 36 DQ12 38 DQ13 39 DQ14 40 DQ15 41
C21 G34
& 31 Z31
23,21D 25
A,22D ∇26,27
23C32 24,25EN27 34,25EN37
A, Z26
A,32D ∇36,37
A, Z36
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown correspond to the DZ package. ‡ A10 and A11 are NC for TMS4x8160 and TMS4x8160P.
•POST OF.