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TPH3R704PL Dataheets PDF



Part Number TPH3R704PL
Manufacturers Toshiba
Logo Toshiba
Description Silicon N-channel MOSFET
Datasheet TPH3R704PL DatasheetTPH3R704PL Datasheet (PDF)

MOSFETs Silicon N-channel MOS (U-MOS-H) TPH3R704PL 1. Applications • High-Efficiency DC-DC Converters • Switching Voltage Regulators • Motor Drivers 2. Features (1) High-speed switching (2) Small gate charge: QSW = 8.1 nC (typ.) (3) Small output charge: Qoss = 20.2 nC (typ.) (4) Low drain-source on-resistance: RDS(ON) = 3.0 mΩ (typ.) (VGS = 10 V) (5) Low leakage current: IDSS = 10 µA (max) (VDS = 40 V) (6) Enhancement mode: Vth = 1.4 to 2.4 V (VDS = 10 V, ID = 0.2 mA) 3. Packaging and Internal .

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MOSFETs Silicon N-channel MOS (U-MOS-H) TPH3R704PL 1. Applications • High-Efficiency DC-DC Converters • Switching Voltage Regulators • Motor Drivers 2. Features (1) High-speed switching (2) Small gate charge: QSW = 8.1 nC (typ.) (3) Small output charge: Qoss = 20.2 nC (typ.) (4) Low drain-source on-resistance: RDS(ON) = 3.0 mΩ (typ.) (VGS = 10 V) (5) Low leakage current: IDSS = 10 µA (max) (VDS = 40 V) (6) Enhancement mode: Vth = 1.4 to 2.4 V (VDS = 10 V, ID = 0.2 mA) 3. Packaging and Internal Circuit TPH3R704PL SOP Advance 1, 2, 3: Source 4: Gate 5, 6, 7, 8: Drain ©2016 Toshiba Corporation 1 Start of commercial production 2015-10 2016-10-19 Rev.3.0 TPH3R704PL 4. Absolute Maximum Ratings (Note) (Ta = 25  unless otherwise specified) Characteristics Symbol Rating Unit Drain-source voltage VDSS 40 V Gate-source voltage VGSS ±20 Drain current (DC) (Tc = 25 ) (Note 1) ID 92 A Drain current (pulsed) (t = 100 µs) (Note 1) IDP 260 A Power dissipation (Tc = 25 ) PD 81 W Power dissipation (Note 2) PD 3.0 W Power dissipation (Note 3) PD 0.96 W Single-pulse avalanche energy (Note 4) EAS 14 mJ Single-pulse avalanche current (Note 4) IAS 92 A Channel temperature Tch 175  Storage temperature Tstg -55 to 175  Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). 5. Thermal Characteristics Characteristics Channel-to-case thermal resistance (Tc = 25 ) Channel-to-ambient thermal resistance (Ta = 25 ) (Note 2) Channel-to-ambient thermal resistance (Ta = 25 ) (Note 3) Note 1: Ensure that the channel temperature does not exceed 175 . Note 2: Device mounted on a glass-epoxy board (a), Figure 5.1 Note 3: Device mounted on a glass-epoxy board (b), Figure 5.2 Note 4: VDD = 32 V, Tch = 25  (initial), L = 1.3 µH, IAS = 92 A Symbol Rth(ch-c) Rth(ch-a) Rth(ch-a) Max Unit 1.83 /W 50 156 Fig. 5.1 Device Mounted on a Glass-Epoxy Board (a) Fig. 5.2 Device Mounted on a Glass-Epoxy Board (b) Note: This transistor is sensitive to electrostatic discharge and should be handled with care. ©2016 Toshiba Corporation 2 2016-10-19 Rev.3.0 TPH3R704PL 6. Electrical Characteristics 6.1. Static Characteristics (Ta = 25  unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit Gate leakage current IGSS VGS = ±20 V, VDS = 0 V   ±0.1 µA Drain cut-off current IDSS VDS = 40 V, VGS = 0 V   10 Drain-source breakdown voltage V(BR)DSS ID = 10 mA, VGS = 0 V 40   V Drain-source breakdown voltage (Note 5) V(BR)DSX ID = 10 mA, VGS = -20 V 25   Gate threshold voltage Vth VDS = 10 V, ID = 0.2 mA 1.4  2.4 Drain-source on-resistance RDS(ON) VGS = 4.5 V, ID = 13 A  4.2 6.0 mΩ VGS = 10 V, ID = 46 A  3.0 3.7 Note 5: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drainsource breakdown voltage is lowered in this mode. 6.2. Dynamic Characteristics (Ta = 25  unless otherwise specified) Characteristics Input capacitance Reverse transfer capacitance Output capacitance Gate resistance Switching time (rise time) Switching time (turn-on time) Switching time (fall time) Switching time (turn-off time) Symbol Ciss Crss Coss rg tr ton tf toff Test Condition VDS = 20 V, VGS = 0 V, f = 1 MHz  See Fig. 6.2.1 Min Typ. Max Unit  1910 2500 pF  41 80  470   0.9 1.4 Ω  5.3  ns  14.7   6.2   24  VDD ≈ 20 V VGS = 0 V/ 10 V ID = 46 A RL = 0.43 Ω RGG = 4.7 Ω RGS = 4.7 Ω Duty ≤ 1 %, tw = 10 µs Fig. 6.2.1 Switching Time Test Circuit 6.3. Gate Charge Characteristics (Ta = 25  unless otherwise specified) Characteristics Total gate charge (gate-source plus gate-drain) Gate-source charge 1 Gate-drain charge Gate switch charge Output charge Symbol Qg Qgs1 Qgd QSW Qoss Test Condition VDD ≈ 20 V, VGS = 10 V, ID = 46 A VDD ≈ 20 V, VGS = 4.5 V, ID = 13 A VDD ≈ 20 V, VGS = 10 V, ID = 46 A VDS = 20 V, VGS = 0 V, f = 1MHz Min Typ. Max Unit  27   13.3   7.7   4.2   8.1   20.2  nC ©2016 Toshiba Corporation 3 2016-10-19 Rev.3.0 TPH3R704PL 6.4. Source-Drain Characteristics (Ta = 25  unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit Reverse drain current (pulsed) (Note 6) IDRP  (t = 100 µs) Diode forward voltage VDSF IDR = 92 A, VGS = 0 V Re.


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