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TMS417400A Dataheets PDF



Part Number TMS417400A
Manufacturers Texas Instruments
Logo Texas Instruments
Description DYNAMIC RANDOM-ACCESS MEMORIES
Datasheet TMS417400A DatasheetTMS417400A Datasheet (PDF)

This data sheet is applicable to all TMS41x400As symbolized by Revision “B”, Revision “E” and subsequent revisions as described in the device symbolization section. D Organization . . . 4 194304 × 4 D Single 5-V Power Supply (±10% Tolerance) D 2 048-Cycle Refresh in 32 ms for TMS417400A D 4 096-Cycle Refresh in 64 ms for TMS416400A D Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC MAX tCAC MAX tAA CYCLE MAX MIN ’41x400A-50 50 ns 13 ns 25 ns 90 ns ’41x400A-60 6.

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This data sheet is applicable to all TMS41x400As symbolized by Revision “B”, Revision “E” and subsequent revisions as described in the device symbolization section. D Organization . . . 4 194304 × 4 D Single 5-V Power Supply (±10% Tolerance) D 2 048-Cycle Refresh in 32 ms for TMS417400A D 4 096-Cycle Refresh in 64 ms for TMS416400A D Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME TIME TIME WRITE tRAC MAX tCAC MAX tAA CYCLE MAX MIN ’41x400A-50 50 ns 13 ns 25 ns 90 ns ’41x400A-60 60 ns 15 ns 30 ns 110 ns ’41x400A-70 70 ns 18 ns 35 ns 130 ns D Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR) Refresh D 3-State Unlatched Output D Low Power Dissipation D High-Reliability Plastic 24 / 26-Lead 300-Mil-Wide Surface-Mount Small-Outline J-Lead (SOJ) Package (DJ Suffix) D Ambient Temperature Range: 0°C to 70°C TMS416400A, TMS417400A 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997 DJ PACKAGE ( TOP VIEW ) VCC DQ1 DQ2 W RAS A11† 1 2 3 4 5 6 26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE 21 A9 A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 A8 18 A7 17 A6 16 A5 15 A4 14 VSS PIN NOMENCLATURE A[0: 11]† CAS DQ[1:4] OE NC RAS VCC VSS W Address Inputs Column-Address Strobe Data In / Data Out Output Enable No Internal Connection Row-Address Strobe 5-V Supply Ground Write Enable † A11 is NC for TMS417400A description The TMS41x400A is a set of 16 777 216-bit dynamic random-access memory (DRAMs) devices organized as 4 194 304 words of 4 bits each. The TMS41x400A employs state-of-the-art technology for high performance, reliability, and low power. These devices feature maximum RAS access times of 50-, 60-, and 70 ns. All address and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS416400A and TMS417400A are offered in a 24 / 26-lead plastic surface-mount SOJ package (DJ suffix). This package is designed for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1997, Texas Instruments Incorporated •POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 1 TMS416400A, TMS417400A 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997 logic symbol (TMS416400A)† A0 9 A1 10 A2 11 A3 12 A4 15 A5 16 A6 17 A7 18 A8 19 A9 21 A10 8 A11 6 RAS 5 23 CAS 4 W 22 OE RAM 4096 K × 4 20D10/21D0 A0 4 194 303 20D19/21D9 20D20 20D21 C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 & 23C22 23,21D G25 24,25 EN 2 DQ1 DQ2 DQ3 DQ4 3 24 25 A,22D 26 A,Z26 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12. •2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 logic symbol (TMS417400A)† A0 9 A1 10 A2 11 A3 12 A4 15 A5 16 A6 17 A7 18 A8 19 A9 21 A10 8 TMS416400A, TMS417400A 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997 RAM 4096 K × 4 20D11/21D0 A0 4 194 303 20D21/21D10 RAS 5 23 CAS 4 W 22 OE C20 [ROW] G23/[REFRESH ROW] 24 [PWR DWN] C21[COLUMN] G24 & 23C22 23,21D G25 24,25 EN 2 DQ1 DQ2 DQ3 DQ4 3 24 25 A,22D 26 A,Z26 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 647-12. •POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 3 TMS416400A, TMS417400A 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997 functional block diagram TMS416400A RAS CAS W OE Timing and Control A0 A1 10 Column- Address Buffers† A11 Column Decode Sense Amplifiers R 256K Array o 256K Array w RowAddress Buffers 12 D e c o d e 12 256K Array † Column addresses A10 and A11 are not used. 4 4 64 I/O Buffers DataIn Reg. 4 DataOut Reg. 4 DQ1 – DQ4 TMS417400A A0 A1 11 ColumnAddress Buffers A10 RowAddress Buffers 11 RAS CAS W OE Timing and Control Column Decode Sense Amplifiers 4 256K Array R 256K Array 256K Array o 256K Array w 4 I/O D Buffers 32 e 32 c o d 256K Array e 256K Array 11 DataIn Reg. 4 DataOut Reg. 4 DQ1 – DQ4 •4 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 TMS416400A, TMS417400A 4194304 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES SMKS889B – AUGUST 1996 – REVISED OCTOBER 1997 operation enhanced page mode Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum number of columns that can be accessed is determined by.


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