TMS417800A

This data sheet is applicable to all TMS417800As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section. D Organization . . . 2 097152 × 8 D Single 5-V Power Supply (± 10% Tolerance) D 2 048-Cycle Refresh in 32 ms D Performance Ranges: ACCESS ACCESS ACCESS READ OR TIME tRAC MAX TIME tCAC MAX TIME tAA MAX EDO CYCLE MIN ’417800A-50 ’417800A-60 50 ns 13 ns 60 ns 15 ns 25 ns 30 ns 20 ns 25 ns ’417800A-70 70 ns 18 ns 35 ns 30 ns D Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR) Refresh D High-Impedance State Unlatched Output D Low Power Dissipation D High-Reliability Plastic 28-Lead 400-Mil-Wide Surface-Mount Small Outline J-Lead (SOJ) Package (DZ Suffix) D Ambient Temperature Range 0°C to 70°C description The TMS417800A is a 16 777 216-bit dynamic random-access memory (DRAM) device organized as 2 097 152 words of eight bits. It employs TI’s state-of-the-art technology for high performance, reliability, and low power. This device features maximum RAS access times of 50-, 60-, and 70 ns. All addresses and data-in lines are latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility. The TMS417800A is offered in a 28-lead plastic surface-mount SOJ package (DZ suffix). This package is designed for operation from 0°C to 70°C. TMS417800A 2097152 BY 8-BIT DYNAMIC RANDOM-ACCESS MEMORY SMKS888B – AUGUST 1996 – REVISED SEPTEMBER 1997 DZ PACKAGE ( TOP VIEW ) VCC DQ0 DQ1 DQ2 DQ3 ...