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SN54HC164 Dataheets PDF



Part Number SN54HC164
Manufacturers Texas Instruments
Logo Texas Instruments
Description 8-Bit Parallel-Out Serial Shift Registers
Datasheet SN54HC164 DatasheetSN54HC164 Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54HC164, SN74HC164 SCLS115G – DECEMBER 1982 – REVISED SEPTEMBER 2015 SNx4HC164 8-Bit Parallel-Out Serial Shift Registers 1 Features •1 Wide Operating Voltage Range of 2 V to 6 V • Outputs Can Drive Up to 10 LSTTL Loads • Low Power Consumption, 80-μA Maximum ICC • Typical tpd = 20 ns • ±4-mA Output Drive at 5 V • Low Input Current of 1-μA Maximum • AND-Gated (Enable/Disable) Serial Inputs • Fully Buffered.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN54HC164, SN74HC164 SCLS115G – DECEMBER 1982 – REVISED SEPTEMBER 2015 SNx4HC164 8-Bit Parallel-Out Serial Shift Registers 1 Features •1 Wide Operating Voltage Range of 2 V to 6 V • Outputs Can Drive Up to 10 LSTTL Loads • Low Power Consumption, 80-μA Maximum ICC • Typical tpd = 20 ns • ±4-mA Output Drive at 5 V • Low Input Current of 1-μA Maximum • AND-Gated (Enable/Disable) Serial Inputs • Fully Buffered Clock and Serial Inputs • Direct Clear • On Products Compliant to MIL-PRF-38535, All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters. 2 Applications • Programable Logic Controllers • Appliances • Video Display Systems • Output Expander 3 Description These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SOIC (14) 8.65 mm × 3.91 mm SN74HC164 PDIP (14) SO (14) 19.30 mm × 6.35 mm 10.30 mm × 5.30 mm TSSOP (14) 5.00 mm × 4.40 mm CDIP (14) 19.94 mm × 6.92 mm SN54HC164 CFP (14) 9.21 mm × 6.29 mm LCCC (14) 9.39 mm × 9.39 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Logic Diagram (Positive Logic) 8 CLK 1 A 2 B C1 1D R C1 1D R C1 1D R 9 CLR 3 45 QA QB QC Pin numbers shown are for the D, J, N, NS, PW, and W packages. C1 1D R 6 QD C1 1D R 10 QE C1 1D R 11 QF C1 1D R 12 QG C1 1D R 13 QH 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC164, SN74HC164 SCLS115G – DECEMBER 1982 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 Features .................................................................. 1 2 Applications ........................................................... 1 3 Description ............................................................. 1 4 Revision History..................................................... 2 5 Device Comparison Table..................................... 3 6 Pin Configuration and Functions ......................... 4 7 Specifications......................................................... 6 7.1 Absolute Maximum Ratings ...................................... 6 7.2 ESD Ratings ..........................


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