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R5F56106WDBG Dataheets PDF



Part Number R5F56106WDBG
Manufacturers Renesas
Logo Renesas
Description 32-Bit MCU
Datasheet R5F56106WDBG DatasheetR5F56106WDBG Datasheet (PDF)

Datasheet RX610 Group Datasheet RENESAS 32-Bit MCU R01DS0097EJ0120 Rev.1.20 Feb 20, 2013 1. Overview 1.1 Features The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with the inclusion of a single-precision floating-point calculation unit as well as a 32-bit multiplier and divider. Additionally, code efficiency is improved by instructions with le.

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Datasheet RX610 Group Datasheet RENESAS 32-Bit MCU R01DS0097EJ0120 Rev.1.20 Feb 20, 2013 1. Overview 1.1 Features The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with the inclusion of a single-precision floating-point calculation unit as well as a 32-bit multiplier and divider. Additionally, code efficiency is improved by instructions with lengths that are variable in byte units and by an enhanced range of addressing modes. Timers, serial communication interfaces, I2C bus interfaces, an A/D converter, and a D/A converter are incorporated as peripheral functions which are essential to embedded devices. Facilities for connecting external memory are also included, enabling direct connection to memory and peripheral LSI circuits. The on-chip memory is flash memory capable of large-capacity, high-speed operation, and this significantly reduces the cost of configuring systems. 1.1.1 Applications Office automation equipment and digital industrial equipment R01DS0097EJ0120 Rev.1.20 Feb 20, 2013 Page 1 of 84 RX610 Group 1.1.2 Outline of Specifications Table 1.1 lists the specifications of the RX610 Group in outline. 1. Overview Table 1.1 Outline of Specifications Classification Module/Function Description CPU CPU Memory FPU Flash RAM Data flash MCU operating modes Clock Clock generation circuit Power down Power-down function • Maximum operating frequency: 100 MHz • 32-bit RX CPU • Minimum instruction execution time: One instruction in one state (in one system clock cycle) • Address space: 4-Gbyte linear address • Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register • Basic instructions: 73 • Floating-point operation instructions: 8 • DSP instructions: 9 • Addressing modes: 10 • Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian • On-chip 32-bit multiplier: 32 x 32 → 64 bits • On-chip divider: 32 / 32 → 32 bits • Barrel shifter: 32 bits • Single precision (32-bit) floating point • Data types and floating-point exceptions conforming to the IEEE754 standard • Flash capacity: 2 Mbytes (max.) • Three types of on-board programming modes SCI boot mode, user program mode, and user boot mode RAM capacity: 128 Kbytes Data flash capacity: 32 Kbytes Single-chip mode, on-chip ROM enabled extended mode, and on-chip ROM disabled extended mode • One main clock oscillation circuit • Includes a PLL circuit and frequency divider, so the operating frequency is selectable • System clock, peripheral module clock, and external bus clock are independently specifiable. The CPU, DMAC, DTC, ROM, and RAM run in synchronization with the system clock (ICLK): 8 to 100 MHz Peripheral modules run in synchronization with the peripheral module clock (PCLK): 8 to 50 MHz Devices connected to the external bus run in synchronization with the external bus clock (BCLK): 8 to 25 MHz • Module stop function • Four power-down modes Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode R01DS0097EJ0120 Rev.1.20 Feb 20, 2013 Page 2 of 84 RX610 Group 1. Overview Classification Interrupt Module/Function Interrupt control unit External bus extension DMA DMA controller Data transfer controller I/O ports Programmable I/O ports Timer 16-bit timer pulse unit Programmable pulse generator 8-bit timer Compare match timer Description • Peripheral function interrupts: 116 • External interrupts: 16 (pins IRQ15 to IRQ0) • Non-maskable interrupt: 1 (the NMI pin) • Eight priority orders specifiable • The external address space can be divided into eight areas (CS0 to CS7), each of which is independently controllable. Capacity of each area: 16 Mbytes Chip-select signals (CS0# to CS7#) can be output for each area. 8-bit or 16-bit bus space can be specified for each area. The data arrangement is selectable as little endian or big endian for each area. (only for data) • Separate bus system • Wait control • Write buffer programming • 4-channel DMA transfer available • Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions • Three transfer modes: Normal transfer, repeat transfer, and block transfer • Activated by interrupt requests (chain transfer enabled) • I/O pins: 117 (144-pin LQFP), 140 (176-pin LFBGA) • Pull-up resistors: 40 • Open-drain outputs: 16 • 5-V tolerance: 10 • (16 bits x 6 channels) x 2 units • Up to 16 pulse inputs and outputs • Select from among 7 or 8 counter-input clocks for each channel • Input capture/output compare function • Maximum of 15-phase PWM output possible in PWM mode • Buffered operation, phase counting mode (two-phase encoder input), and cascaded operation (32 bit.


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