TMS626162A

TMS626162A 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS692B – JULY 1997 – REVISED MARCH 1998 D Organization 512K × 16 Bits × 2 Banks D 3.3-V Power Supply (± 10% Tolerance) D Two Banks for On-Chip Interleaving (Gapless Accesses) D High Bandwidth – Up to 100-MHz Data Rates D CAS Latency (CL) Programmable to Two or Three Cycles From Column-Address Entry D Burst Sequence Programmable to Serial or Interleave D Burst Length Programmable to 1, 2, 4, 8, or Full Page D Chip Select and Clock Enable for Enhanced-System Interfacing D Cycle-by-Cycle DQ-Bus Mask Capability With Upper- and Lower-Byte Control D Auto-Refresh and Self-Refresh Capability D 4K Refresh (Total for Both Banks) D High-Speed, Low-Noise, Low-Voltage TTL (LVTTL) Interface D Power-Down Mode D Compatible With JEDEC Standards D Pipeline Architecture D Temperature Ranges: Operating, 0°C to 70°C Storage, – 55°C to 150°C DGE PACKAGE ( TOP VIEW ) VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ DQML W CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 VSS 49 DQ15 48 DQ14 47 VSSQ 46 DQ13 45 DQ12 44 VCCQ 43 DQ11 42 DQ10 41 VSSQ 40 DQ9 39 DQ8 38 VCCQ 37 NC 36 DQMU 35 CLK 34 CKE 33 NC 32 A9 31 A8 30 A7 29 A6 28 A5 27 A4 26 VSS SYNCHRONOUS CLOCK CYLE TIME tCK3 tCK2 (CL† = 3) (CL = 2) ’626162A-10 10 ns † CL = CAS latency 15 ns ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 (CL = 3) (CL = 2) 7 ns 7 ns REFRESH INTERVAL tREF 64 ms descri...