RANDOM-ACCESS MEMORY. TMS626162A Datasheet

TMS626162A MEMORY. Datasheet pdf. Equivalent

Part TMS626162A
Description SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
Feature TMS626162A 524288 BY 16-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS692B – JULY 1997 .
Manufacture etcTI
Total Page 30 Pages
Datasheet
Download TMS626162A Datasheet



TMS626162A
TMS626162A
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS692B – JULY 1997 – REVISED MARCH 1998
D Organization
512K × 16 Bits × 2 Banks
D 3.3-V Power Supply (± 10% Tolerance)
D Two Banks for On-Chip Interleaving
(Gapless Accesses)
D High Bandwidth – Up to 100-MHz Data
Rates
D CAS Latency (CL) Programmable to Two or
Three Cycles From Column-Address Entry
D Burst Sequence Programmable to Serial or
Interleave
D Burst Length Programmable to 1, 2, 4, 8, or
Full Page
D Chip Select and Clock Enable for
Enhanced-System Interfacing
D Cycle-by-Cycle DQ-Bus Mask Capability
With Upper- and Lower-Byte Control
D Auto-Refresh and Self-Refresh Capability
D 4K Refresh (Total for Both Banks)
D High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
D Power-Down Mode
D Compatible With JEDEC Standards
D Pipeline Architecture
D Temperature Ranges:
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
DGE PACKAGE
( TOP VIEW )
VCC
DQ0
DQ1
VSSQ
DQ2
DQ3
VCCQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VCCQ
DQML
W
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 VSS
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VCCQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VCCQ
37 NC
36 DQMU
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
SYNCHRONOUS
CLOCK CYLE
TIME
tCK3
tCK2
(CL= 3) (CL = 2)
’626162A-10
10 ns
CL = CAS latency
15 ns
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
tAC2
(CL = 3) (CL = 2)
7 ns 7 ns
REFRESH
INTERVAL
tREF
64 ms
description
The TMS626162A is a high-speed 16 777 216-bit
synchronous dynamic random-access memory
(SDRAM) device organized as two banks of
524 288 words with 16 bits per word.
A[0: 10]
A11
CAS
CKE
CLK
CS
DQ[0 : 15]
DQML, DQMU
NC
RAS
VCC
VCCQ
VSS
VSSQ
W
PIN NOMENCLATURE
Address Inputs
A0 – A10 Row Addresses
A0 – A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
System Clock
Chip Select
SDRAM Data Input / Output
Data Input / Output Mask Enable
No Connect
Row-Address Strobe
Power Supply (3.3-V Typical)
Power Supply for Output Drivers
(3.3-V Typical)
Ground
Ground for Output Drivers
Write Enable
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1998, Texas Instruments Incorporated
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
1



TMS626162A
TMS626162A
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS692B – JULY 1997 – REVISED MARCH 1998
description (continued)
All inputs and outputs of the TMS626162A series are compatible with the LVTTL interface.
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed
microprocessors and caches.
The TMS626162A SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).
functional block diagram
CLK
CKE
CS
DQMx
RAS
CAS
W
A0 – A11
12
Control
Array Bank T
Array Bank B
DQ
Buffer
DQ0 – DQ15
16
Mode Register
operation
All inputs to the ’626162A SDRAM are latched on the rising edge of the system (synchronous) clock. The
outputs, DQ0 – DQ15, are also referenced to the rising edge of CLK. The ’626162A has two banks that are
accessed independently. A bank must be activated before it can be accessed (read from or written to). Refresh
cycles refresh both banks alternately.
Six basic commands or functions control most operations of the ’626162A:
D Bank activate/row-address entry
D Column-address entry/write operation
D Column-address entry/read operation
D Bank deactivate
D Auto-refresh
D Self-refresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select / deselect the
devices, using data/output mask enables (DQMx) to enable/mask the DQ signals on a cycle-by-cycle basis, or
using clock enable (CKE) to suspend the system clock (CLK) input. The device contains a mode register that
must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’626162A. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
2 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)