TMS626812

TMS626812 1048576 BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS687A –JULY 1996 – REVISED APRIL 1997 D Organization . . . 1M × 8 × 2 Banks D 3.3-V Power Supply (± 10% Tolerance) D Two Banks for On-Chip Interleaving (Gapless Accesses) D High Bandwidth – Up to 83-MHz Data Rates D CAS Latency Programmable to 2 or 3 Cycles From Column-Address Entry D Burst Sequence Programmable to Serial or Interleave D Burst Length Programmable to 1, 2, 4, or 8 D Chip Select and Clock Enable for Enhanced-System Interfacing D Cycle-by-Cycle DQ-Bus Mask Capability D Auto-Refresh and Self-Refresh Capability D 4K Refresh (Total for Both Banks) D High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface D Power-Down Mode D Compatible With JEDEC Standards D Pipeline Architecture D Temperature Ranges Operating, 0°C to 70°C Storage, – 55°C to 150°C D Performance Ranges: DGE PACKAGE ( TOP VIEW ) VCC DQ0 VSSQ DQ1 VCCQ DQ2 VSSQ DQ3 VCCQ NC NC W CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 VSS 43 DQ7 42 VSSQ 41 DQ6 40 VCCQ 39 DQ5 38 VSSQ 37 DQ4 36 VCCQ 35 NC 34 NC 33 DQM 32 CLK 31 CKE 30 NC 29 A9 28 A8 27 A7 26 A6 25 A5 24 A4 23 VSS SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 (CL = 3) (CL = 2) ACCESS TIME CLOCK TO OUTPUT tCK3 tCK2 (CL = 3) (CL = 2) ’626812-12A† 12 ns 15 ns 9 ns 9 ns ’626812-12 12 ns 18 ns 9 ns 10 ns † –12A speed device is supported only at –5/+10% VCC REFRESH INTERVAL 64 ms 64 ms description The TMS626...