PRE-FET DRIVER. TPIC46L01 Datasheet

TPIC46L01 DRIVER. Datasheet pdf. Equivalent

Part TPIC46L01
Description 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
Feature TPIC46L01, TPIC46L02, TPIC46L03 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER D 6-Channel S.
Manufacture etcTI
Total Page 19 Pages
Datasheet
Download TPIC46L01 Datasheet



TPIC46L01
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
D 6-Channel Serial-in/Parallel-in Low-side
Pre-FET Driver
D Device Can Be Cascaded
D Internal 55-V Inductive Load Clamp and
VGS Protection Clamp for External Power
FETs
D Independent Shorted-Load/Short-to-Battery
Fault Detection on All Drain Terminals
D Independent Off-State Open-Load Fault
Sense
D Over-Battery-Voltage Lockout Protection
and Fault Reporting
D Under-Battery-Voltage Lockout Protection
for TPIC46L01 and TPIC46L02
D Asynchronous Open-Drain Fault Flag
D Device Output Can be Wire-ORed with
Multiple External Devices
D Fault Status Returned Through Serial
Output Terminal
D Internal Global Power-on Reset of Device
D High-Impedance CMOS Compatible Inputs
With Hysteresis
D TPIC46L01 and TPIC46L03 Disables the
Gate Output When a Shorted-Load Fault
Occurs
D TPIC46L02 Transitions the Gate Output to a
Low-Duty-Cycle PWM Mode When a
Shorted-Load Fault Occurs
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
DB PACKAGE
(TOP VIEW)
FLT
VCOMPEN
VCOMP
IN0
IN1
IN2
IN3
IN4
IN5
CS
SDO
SDI
SCLK
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VBAT
27 GATE0
26 DRAIN0
25 GATE1
24 DRAIN1
23 DRAIN2
22 GATE2
21 GATE3
20 DRAIN3
19 DRAIN4
18 GATE4
17 DRAIN5
16 GATE5
15 GND
description
The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and
parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the
TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive
load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format.
Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery
detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load
faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient
protection for the external FET.
These devices provide control of output channels through a serial input interface or a parallel input interface.
A command to enable the output from either interface enables the respective channel GATE output to the
external FET. The serial input interface is recommended when the number of signals between the control device
and the predriver must be minimized, and the speed of operation is not critical. In applications where the
predriver must respond very quickly or asynchronously, the parallel input interface is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1997, Texas Instruments Incorporated
1



TPIC46L01
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
For serial operation, the control device must transition CS from high to low to activate the serial input interface.
When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT flag is
refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must
consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns
it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data
consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03) and
shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates
a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared
asynchronously to reflect the current state of the hardware. The fault must be present when CS is transitioned
from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial
register when CS is low. CS must be transitioned high after all of the serial data has been clocked into the device.
A low-to-high transition of CS transfers the last six bits of serial data to the output buffer, puts SDO in a
high-impedance state, and clears and re-enables the fault register. The TPIC46L01/L02/L03 was designed to
allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the
controller. Serial input data flows through the device and is transferred out SDO following the fault data in
cascaded configurations.
For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to
the respective GATE output. SCLK or CS are not required for parallel control. A 1 on the parallel input turns the
respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can
enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is
selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN
to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect
shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault
occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT as well
as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel
transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be
flagged as a fault. A fault signal is sent to FLT as well as the serial fault register bit. More detail on fault detection
operation is presented in the device operation section of this data sheet.
The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage
conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery
voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the
overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no
undervoltage threshold), all channels are disabled and a fault signal is sent to FLT as well as to the respective
fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected.
When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables
fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are
re-enabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET. This clamp voltage is defined by the sum of VC and turn-on voltage of the external FET. The predriver
also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from
exceeding their rated voltages.
These devices provide pulldown resistors on all inputs except CS. A pullup resistor is used on CS.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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