CD74ACT74

CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCHS321 – DECEMBER 2002 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54ACT74 . . . F PACKAGE CD74ACT74 . . . E OR M PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 2 3 4 5 6 7 14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q description/ordering information The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74ACT74E CD74ACT74E –55°C to 125°C SOIC – M Tube CD74ACT74M Tape and reel CD74ACT74M96 ACT74M CDIP – F Tube CD54ACT74F3A CD54ACT74F3A † Package drawings, standard packing...