BUFFER GATES. SN74ABT125 Datasheet

SN74ABT125 GATES. Datasheet pdf. Equivalent

Part SN74ABT125
Description QUADRUPLE BUS BUFFER GATES
Feature D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C D High-Drive Outputs (−32-mA IOH,.
Manufacture etcTI
Total Page 27 Pages
Datasheet
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SN74ABT125
D Typical VOLP (Output Ground Bounce)
<1 V at VCC = 5 V, TA = 25°C
D High-Drive Outputs (−32-mA IOH, 64-mA IOL)
D Ioff and Power-Up 3-State Support Hot
Insertion
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002
D Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54ABT125 . . . J OR W PACKAGE
SN74ABT125 . . . D, DB, N, NS,
OR PW PACKAGE
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
SN74ABT125 . . . RGY PACKAGE
(TOP VIEW)
1A
1Y
2OE
2A
2Y
2
3
4
5
6
1
7
14
13
12
11
10
9
8
4OE
4A
4Y
3OE
3A
SN54ABT125 . . . FK PACKAGE
(TOP VIEW)
1Y
NC
2OE
NC
2A
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
4A
NC
4Y
NC
3OE
description/ordering information
NC − No internal connection
The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is
disabled when the associated output-enable (OE) input is high.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube
SN74ABT125N
SN74ABT125N
−40°C to 85°C
QFN − RGY
SOIC − D
SOP − NS
SSOP − DB
Tape and reel
Tube
Tape and reel
Tape and reel
Tape and reel
SN74ABT125RGYR
SN74ABT125D
SN74ABT125DR
SN74ABT125NSR
SN74ABT125DBR
AB125
ABT125
ABT125
AB125
TSSOP − PW Tape and reel SN74ABT125PWR AB125
CDIP − J
Tube
SNJ54ABT125J
SNJ54ABT125J
−55°C to 125°C CFP − W
Tube
SNJ54ABT125W
SNJ54ABT125W
LCCC − FK
Tube
SNJ54ABT125FK SNJ54ABT125FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



SN74ABT125
SN54ABT125, SN74ABT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002
FUNCTION TABLE
(each buffer)
INPUTS
OE A
OUTPUT
Y
LH
H
LL
L
HX
Z
logic diagram (positive logic)
1OE 1
2
1A
3
1Y
3OE 10
9
3A
8
3Y
2OE 4
5
2A
6
2Y
4OE 13
12
4A
Pin numbers shown are for the D, DB, J, N, NS, PW, RGY, and W packages.
11
4Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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