SN74ABT125

D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C D High-Drive Outputs (−32-mA IOH, 64-mA IOL) D Ioff and Power-Up 3-State Support Hot Insertion SN54ABT125, SN74ABT125 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS182I − FEBRUARY 1997 − REVISED NOVEMBER 2002 D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN54ABT125 . . . J OR W PACKAGE SN74ABT125 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1OE 1A 1Y 2OE 2A 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y SN74ABT125 . . . RGY PACKAGE (TOP VIEW) 1OE VCC 1A 1Y 2OE 2A 2Y 2 3 4 5 6 1 7 14 13 12 11 10 9 8 4OE 4A 4Y 3OE 3A SN54ABT125 . . . FK PACKAGE (TOP VIEW) 1A 1OE NC VCC 4OE 1Y NC 2OE NC 2A 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A GND 3Y description/ordering information NC − No internal connection The ’ABT125 quadruple bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driv...