MONOSTABLE MULTIVIBRATORS. SN54LS221 Datasheet

SN54LS221 MULTIVIBRATORS. Datasheet pdf. Equivalent

Part SN54LS221
Description DUAL MONOSTABLE MULTIVIBRATORS
Feature D Dual Versions of Highly Stable SN54121 and SN74121 One Shots D SN54221 and SN74221 Demonstrate Ele.
Manufacture etcTI
Total Page 27 Pages
Datasheet
Download SN54LS221 Datasheet



SN54LS221
D Dual Versions of Highly Stable SN54121
and SN74121 One Shots
D SN54221 and SN74221 Demonstrate
Electrical and Switching Characteristics
That Are Virtually Identical to the SN54121
and SN74121 One Shots
D Pinout Is Identical to the SN54123,
SN74123, SN54LS123, and SN74LS123
D Overriding Clear Terminates Output Pulse
TYPE
SN54221
SN74221
SN54LS221
SN74LS221
MAXIMUM
OUTPUT
PULSE
LENGTH(S)
21
28
49
70
description/ordering information
The ’221 and ’LS221 devices are dual
multivibrators with performance characteristics
virtually identical to those of the ’121 devices.
Each multivibrator features a negative-transition-
triggered input and a positive-transition-triggered
input, either of which can be used as an inhibit
input.
SN54221, SN54LS221, SN74221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITTĆTRIGGER INPUTS
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
SN54221, SN54LS221 . . . J PACKAGE
SN74221 . . . N PACKAGE
SN74LS221 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
1A
1B
1CLR
1Q
2Q
2Cext
2Rext/Cext
GND
1
2
3
4
5
6
7
8
16 VCC
15 1Rext/Cext
14 1Cext
13 1Q
12 2Q
11 2CLR
10 2B
9 2A
SN54LS221 . . . FK PACKAGE
(TOP VIEW)
1CLR
1Q
NC
2Q
2Cext
3 2 1 20 19
4 18
5 17
6 16
7 15
8 14
9 10 11 12 13
1Cext
1Q
NC
2Q
2CLR
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube
SN74221N
SN74LS221N
SN74221N
SN74LS221N
0°C to 70°C
SOIC − D
Tube
Tape and reel
SN74LS221D
SN74LS221DR
LS221
SOP − NS
Tape and reel SN74LS221NSR
74LS221
SSOP − DB
Tape and reel SN74LS221DBR
LS221
CDIP − J
−55°C to 125°C
Tube
SNJ54221J
SNJ54LS221J
SNJ54221J
SNJ54LS221J
LCCC − FK
Tube
SNJ54LS221FK
SNJ54LS221FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2004, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1



SN54LS221
SN54221, SN54LS221, SN74221, SN74LS221
DUAL MONOSTABLE MULTIVIBRATORS
WITH SCHMITTĆTRIGGER INPUTS
SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 kand Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and
temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kto 30 kfor the SN54221,
2 kto 40 kfor the SN74221, 2 kto 70 kfor the SN54LS221, and 2 kto 100 kfor the SN74LS221).
Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 0.7 CextRext. In
circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 k
can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air
temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher
duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width
versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by
merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.
FUNCTION TABLE
(each monostable multivibrator)
INPUTS
OUTPUTS
CLR A B Q Q
LXXLH
XHX L H
XXL LH
HL
††
HH
††
L
H
††
Pulsed-output patterns are tested during
AC switching at 25°C with Rext = 2 k, and
Cext = 80 pF.
This condition is true only if the output of
the latch formed by the two NAND gates
has been conditioned to the logic 1 state
prior to CLR going high. This latch is
conditioned by taking either A high or
B low while CLR is inactive (high).
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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