LVPECL Oscillator. DSC8122 Datasheet

DSC8122 Oscillator. Datasheet pdf. Equivalent

Part DSC8122
Description Programmable Low-Jitter Precision LVPECL Oscillator
Feature DSC8102 DSC8122 Programmable Low-Jitter Precision LVPECL Oscillator General Description The DSC81.
Manufacture Micrel
Total Page 6 Pages
Datasheet
Download DSC8122 Datasheet



DSC8122
DSC8102 DSC8122
Programmable Low-Jitter Precision LVPECL Oscillator
General Description
The DSC8102 & DSC8122 series of high
performance field-programmable oscillators
utilizes a proven silicon MEMS technology to
provide excellent jitter and stability over a
wide range of supply voltages and
temperatures.
Using the TIMEFLASH
programmer, the end user can easily
program the oscillators’ frequency in the field
for immediate testing or use in advance
prototype development or production.
DSC8102 has a standby feature allowing it to
completely power-down when EN pin is
pulled low; whereas for DSC8122, only the
outputs are disabled when EN is low. Both
oscillators are available in industry standard
packages, including the small 3.2x2.5 mm2,
and are “drop-in” replacement for standard
6-pin LVPECL quartz oscillators.
Block Diagram
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o Industrial: -40° to 85° C
o Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Wide Freq. Range: 10 to 460 MHz
Small Industry Standard Footprints
o 2.5x2.0, 3.2x2.5, 5.0x3.2, & 7.0x5.0 mm
Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
High Reliability
o 20x better MTF than quartz oscillators
Low Current Consumption
Supply Range of 2.25 to 3.6 V
Standby & Output Enable Function
Lead Free & RoHS Compliant
LVDS & HCSL Versions Available
Output Enable Modes
EN Pin
High
NC
Low
DSC8102
Outputs Active
Outputs Active
Standby
DSC8122
Outputs Active
Outputs Active
Outputs Disabled
Applications
Storage Area Networks
o SATA, SAS, Fibre Channel
Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express: Gen 1 & Gen 2
DisplayPort
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Micrel, Inc. Micrel Inc. may update or make changes
to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not limited to
implied warranties of merchantability or fitness for a particular use.
Page 1 |
MK-Q-B-P-D-110410-02-2



DSC8122
DSC8102 DSC8122 Programmable Low-Jitter Precision LVPECL Oscillator
Absolute Maximum Ratings
Item
Min Max Unit
Supply Voltage -0.3 +4.0
V
Input Voltage
Junction Temp
-0.3
-
VDD+0.3
+150
V
°C
Storage Temp -55 +150
°C
Soldering Temp -
+260
°C
ESD
-
HBM
4000
MM 400
CDM
1500
Note: 1000+ years of data retention on internal memory
V
Condition
40sec max.
Specifications
Ordering Code
Enable Modes
0: Enable/Standby
2: Enable/Disable
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
DSC81 0 2 C I 5 -
Package
A: 7.0x5.0mm
B: 5.0x3.2mm
C: 3.2x2.5mm
D: 2.5x2.0 mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
T
Parameter
Condition
Supply Voltage1
Supply Current
Frequency Stability
Aging
Startup Time2
Input Logic Levels
Input logic high
Input logic low
Output Disable Time3
Output Enable Time
Enable Pull-Up Resistor4
VDD
EN pin low outputs are disabled
IDD DSC8102
DSC8122
Includes frequency variations due
Δf to initial tolerance, temp. and
power supply voltage
Δf 1 year @25°C
tSU T=25°C
VIH
VIL
tDA
tEN
DSC8102
DSC8122
Pull-up resistor exist
LVPECL Outputs
Supply Current
IDD Output Enabled, RL=50Ω
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
Pk to Pk Output Swing
Output Transition time3
Rise Time
Fall Time
Frequency
Output Duty Cycle
tR
tF
f0
SYM
Single-Ended
20% to 80%
RL=50Ω, CL= 0pF
Single Frequency
Differential
Period Jitter
JPER
Integrated Phase Noise
200kHz to 20MHz @156.25MHz
JPH 100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
Notes:
1.
2.
3.
4.
Pin 6 VDD should be filtered with 0.1uf capacitor.
tsu is time to 100ppm of output frequency after VDD is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Output is enabled if pad is floated or not connected.
Min.
2.25
0.75xVDD
-
VDD-1.08
-
10
48
Typ.
20
40
56.5
800
250
2.5
0.25
0.38
1.7
Max.
3.6
Unit
V
0.095
22
±10
±25
±50
±5
5
mA
ppm
ppm
ms
-
0.25xVDD
5
5
20
V
ns
ms
ns
kΩ
58 mA
-
VDD-1.55
V
mV
ps
460
52
2
MHz
%
psRMS
psRMS
All Rights Reserved. No part of this document may be copied or reproduced in any form without the prior written permission of Micrel, Inc. Micrel Inc. may update or make changes
to the contents, products, programs or services described at any time without notice. This document neither states nor implies any kind of warranty, including, but not limited to
implied warranties of merchantability or fitness for a particular use.
Page 2 |
MK-Q-B-P-D-110410-02-2





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