Linear Regulator. TPS7A30 Datasheet

TPS7A30 Regulator. Datasheet pdf. Equivalent

Part TPS7A30
Description Negative Linear Regulator
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TPS7A30
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TPS7A30
SBVS125D – AUGUST 2010 – REVISED JUNE 2015
TPS7A30 –35-V, –200-mA, Ultralow-Noise, Negative Linear Regulator
1 Features
1 Input Voltage Range: –3 V to –35 V
• Noise:
– 14 μVRMS (20 Hz to 20 kHz)
– 15.1 μVRMS (10 Hz to 100 kHz)
• Power-Supply Ripple Rejection:
– 72 dB (120 Hz)
55 dB (10 Hz to 700 kHz)
• Adjustable Output: –1.18 V to –33 V
• Maximum Output Current: 200 mA
• Dropout Voltage: 216 mV at 100 mA
• Stable with Ceramic Capacitors 2.2 μF
• CMOS Logic-Level-Compatible Enable Pin
• Built-In, Fixed, Current Limit and Thermal
Shutdown Protection
• Packages: 8-Pin HVSSOP PowerPAD™ and
3-mm × 3-mm VSON
• Operating Temperature Range:
–40°C to 125°C
2 Applications
• Supply Rails for Operational Amplifiers, DACs,
ADCs, and Other High-Precision Analog Circuitry
• Audio
• Post DC-DC Converter Regulation and
Ripple Filtering
• Test and Measurement
• RX, TX, and PA Circuitry
• Industrial Instrumentation
• Base Stations and Telecom Infrastructure
• –12-V and –24-V Industrial Buses
3 Description
The TPS7A30 series of devices are negative, high-
voltage (–35 V), ultralow-noise (15.1 μVRMS, 72-dB
PSRR) linear regulators that can source a maximum
load of 200 mA.
These linear regulators include a CMOS logic-level-
compatible enable pin and capacitor-programmable
soft-start function that allows for customized power-
management schemes. Other features include built-in
current limit and thermal shutdown protection to
safeguard the device and system during fault
conditions.
The TPS7A30 family is designed using bipolar
technology, and is ideal for high-accuracy, high-
precision instrumentation applications where clean
voltage rails are critical to maximize system
performance. This design makes the device an
excellent choice to power operational amplifiers,
analog-to-digital converters (ADCs), digital-to-analog
converters (DACs), and other high-performance
analog circuitry.
In addition, the TPS7A30 family of linear regulators is
suitable for post dc-dc converter regulation. By
filtering out the output voltage ripple inherent to dc-dc
switching conversion, maximum system performance
is provided in sensitive instrumentation, test and
measurement, audio, and RF applications.
For applications that require positive and negative
high-performance rails, consider TI’s TPS7A49 family
of positive high-voltage, ultralow-noise linear
regulators.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS7A30
HVSSOP (8)
VSON (8)
3.00 mm × 3.00 mm
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Post DC-DC Converter Regulation for High-Performance Analog Circuitry
+18V
-18V
IN OUT
+15V
TPS7A49
EN GND
IN OUT
-15V
TPS7A30
EN GND
EVM
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.



TPS7A30
TPS7A30
SBVS125D – AUGUST 2010 – REVISED JUNE 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 ESD Ratings ............................................................ 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information .................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Typical Characteristics .............................................. 8
7 Parameter Measurement Information ................ 13
8 Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
9 Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 20
9.3 Do's and Don’ts....................................................... 23
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Examples................................................... 24
11.3 Thermal Considerations ........................................ 26
11.4 Power Dissipation ................................................. 26
12 Device and Documentation Support ................. 28
12.1 Device Support .................................................... 28
12.2 Documentation Support ....................................... 28
12.3 Community Resources.......................................... 28
12.4 Trademarks ........................................................... 28
12.5 Electrostatic Discharge Caution ............................ 28
12.6 Glossary ................................................................ 29
13 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2015) to Revision D
Page
• Added DRB package to document ......................................................................................................................................... 1
• Added TI Design ..................................................................................................................................................................... 1
• Changed Packages Features bullet ...................................................................................................................................... 1
• Added VSON row to Device Information table ...................................................................................................................... 1
• Added DRB package to Pin Configuration and Functions section ......................................................................................... 4
• Changed EN pin description in Pin Functions table: updated voltage symbols .................................................................... 4
• Added DRB column to Thermal Information table.................................................................................................................. 6
• Changed test conditions of last row in |IEN| parameter of Electrical Characteristics table ..................................................... 7
• Changed title and y-axis of Figure 7 to Ground Current ........................................................................................................ 9
• Changed y-axis of Figure 11 and Figure 12 to IQ .................................................................................................................. 9
• Changed VEN value of disabled mode in Table 1 ................................................................................................................ 16
• Changed first sentence of Application Information section .................................................................................................. 17
• Added Table 2 and respective description to Adjustable Operation section ........................................................................ 17
• Deleted third sentence from Capacitor Recommendations section .................................................................................... 17
• Changed third paragraph of Power for Precision Analog section ....................................................................................... 19
• Changed description of start-up time in Design Requirements section ............................................................................... 20
• Changed Equation 3 ............................................................................................................................................................ 20
• Changed Equation 8 ............................................................................................................................................................ 21
• Changed fifth item in Do's and Don’ts section ..................................................................................................................... 23
• Changed Figure 40 footnote ................................................................................................................................................ 25
• Changed 35°C to 45°C in Thermal Considerations section ................................................................................................ 26
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