LOGIC-LEVEL MOSFETS. TPS1110Y Datasheet

TPS1110Y MOSFETS. Datasheet pdf. Equivalent

Part TPS1110Y
Description SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS
Feature TPS1110, TPS1110Y SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS D Low rDS(on) . . . 65 mΩ Typ at VGS = – 4.5.
Manufacture etcTI
Total Page 14 Pages
Datasheet
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TPS1110Y
TPS1110, TPS1110Y
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS
D Low rDS(on) . . . 65 mTyp at VGS = – 4.5 V
D High Current Capability
6 A at VGS = – 4.5 V
D Logic-Level Gate Drive (3 V Compatible)
VGS(th) = – 0.9 V Max
D Low Drain-Source Leakage Current
< 100 nA From 25°C to 75°C
at VDS = – 6 V
D Fast Switching . . . 5.8 ns Typ td(on)
D Small-Outline Surface-Mount Power
Package
SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998
D PACKAGE
(TOP VIEW)
SOURCE
SOURCE
SOURCE
GATE
1
2
3
4
8 DRAIN
7 DRAIN
6 DRAIN
5 DRAIN
description
The TPS1110 is a single, low-rDS(on), P-channel enhancement-mode power MOS transistor. The device
features extremely low-rDS(on) values coupled with logic-level gate-drive capability and very low drain-source
leakage current. With a maximum VGS(th) of – 0.9 V and an IDSS of only –100 nA, the TPS1110 is the ideal
high-side switch for low-voltage, portable battery-management power-distribution systems where maximizing
battery life is an important concern. The thermal performance of the 8-pin small-outline (D) package has been
greatly enhanced over the standard 8-pin SOIC, further making the TPS1110 ideally suited for many power
applications. For compatibility with existing designs, the TPS1110 has a pinout common with other P-channel
MOSFETs in small-outline integrated circuit (SOIC) packages. The TPS1110 is characterized for an operating
junction temperature range, TJ, from – 40°C to 150°C. The D package is available packaged in standard sleeves
or in taped and reeled formats. When ordering the tape-and-reel format, add an R suffix to the device type
number (e.g., TPS1110DR).
AVAILABLE OPTIONS
PACKAGED DEVICE†
CHIP FORM
TJ
SMALL OUTLINE
(Y)
(D)
– 40°C to 150°C
TPS1110D
TPS1110Y
The D package is available taped and reeled. Add an R suffix to device
type (e.g., TPS1110DR). The chip form is tested at 25°C.
schematic
SOURCE
1 23
GATE 4
5 67 8
DRAIN
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1998, Texas Instruments Incorporated
1



TPS1110Y
TPS1110, TPS1110Y
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS
SLVS100B – OCTOBER 1994 – REVISED JANUARY 1998
TPS1110Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1110C. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(4)
SOURCE (1)
(8) DRAIN
(2) (7)
SOURCE
(3)
SOURCE
TPS1110Y
DRAIN
(6)
DRAIN
(5)
(3)
(4)
GATE
(5)
DRAIN
(6)
57
(8)
(7)
64
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
(1) TJmax = 150°C
TOLERANCES ARE ± 10%
(2)
ALL DIMENSIONS ARE IN MILS
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265





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