Document
TPS2838, TPS2839 TPS2848, TPS2849
ą
SLVS367A − MARCH 2001 − REVISED JUNE 2001
SYNCHRONOUSĆBUCK MOSFET DRIVERS WITH DRIVE REGULATOR
FEATURES
D Integrated Drive Regulator (4 V to 14 V) D Adjustable/Adaptive Dead-Time Control D 4-A Peak current at VDRV of 14 V D 10-V to 15-V Supply Voltage Range D TTL-Compatible Inputs D Internal Schottky Diode Reduces Part Count D Synchronous or Nonsynchronous Operation
D Inverting and Noninverting Options D TSSOP PowerPad Package for Excellent
Thermal Performance
APPLICATIONS
D Single or Multiphase Synchronous-Buck
Power Supplies
D High-Current DC/DC Power Modules
DESCRIPTION
The TPS2838/39/48/49 devices are MOSFET drivers designed for high-performance synchronous power supplies. The drivers can source and sink up to 4-A peak current at a 14-V drive voltage. These are ideal devices to use with power supply controllers that do not have on-chip drivers. The low-side driver is capable of driving loads of 3.3 nF in 10-ns rise/fall times and has 40-ns propagation delays at room temperature.
The MOSFET drivers have an integrated 150-mA regulator, so the gate drive voltage can be optimized for specific MOSFETs. The TPS2848 and TPS2849 have a fixed 8-V drive regulator, while the TPS2838/39 allow the drive regulator to be adjusted from 4 V to 14 V by selection of two external resistors.
The devices feature VDRV to PGND shootthrough protection with adaptive/adjustable deadtime control. The deadtime, for turning on the high-side FET from LOWDR transitioning low, is adjustable with an external capacitor on the DELAY pin. This allows compensation for the effect the gate resistor has on the synchronous FET turn off. The adaptive deadtime prevents the turning on of the low-side FET until the voltage on the BOOTLO pin falls below a threshold after the high-side FET stops conducting. The high-side drive can be configured as a ground referenced driver or a floating bootstrap driver. The internal Schottky diode minimizes the size and number of external components needed for the bootstrap driver circuit. Only one external ceramic capacitor is required to configure the bootstrap driver.
TPS2838, TPS2839 PWP PACKAGE (TOP VIEW)
TPS2848, TPS2849 PWP PACKAGE (TOP VIEW)
ENABLE IN
PWRRDY DELAY SYNC ADJ DT AGND
1 16 2 15 3 14 4 Thermal 13 5 Pad 12 6 11 7 10 89
BOOT HIGHDR BOOTLO VCC VDRV LOWDR NC PGND
ACTUAL SIZE (5,1 mm x 6,6 mm)
ENABLE IN
PWRRDY
DELAY
NC
ACTUAL SIZE
DT
(5,1 mm x 6,6 mm) AGND
1 14
2 13
3 12
4
Thermal Pad
11
5 10
69
78
BOOT HIGHDR BOOTLO VCC VDRV LOWDR PGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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TPS2838, TPS2839 TPS2848, TPS2849 ą
SLVS367A − MARCH 2001 − REVISED JUNE 2001
description (continued) The SYNC pin can be used regardless of load to disable the synchronous FET driver and operate the power supply nonsynchronously. A power ready/undervoltage lockout function outputs the status of the VCC-pin voltage and driver regulator output on the open-drain PWRRDY pin. This feature can be used to enable a controller’s output once the VCC voltage reaches the threshold and the regulator output is stable. This function ensures both FET drivers are off when the VCC voltage is below the voltage threshold. The TPS2838/39/48/49 devices are offered in the thermally enhanced 14-pin and 16-pin PowerPAD TSSOP package. The PowerPAD package features an exposed leadframe on the bottom that can be soldered to the printed-circuit board to improve thermal efficiency. The TPS2838/48 are noninverting control logic while the TPS2839/49 drivers are inverting control logic.
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functional block diagram (TPS2838, TPS2839)
VCC Vr1
ADJ
TPS2838, TPS2839 TPS2848, TPS2849
ą
SLVS367A − MARCH 2001 − REVISED JUNE 2001
VDRV
VCC
PWRRDY AGND
POR
SYS_UVLO
THERMAL SHUTDOWN
SHUTDOWN
0.9 × Vref
DRIVE REGULATOR
REFERENCES
Vref Vr1 0.9 × Vref SHUTDOWN
BOOT
IN
SYNC DT
ENABLE
INVERTING OPTION TPS2839 ONLY
VDRV
SYS_UVLO DEADTIME CONTROL
HIGHDR BOOTLO
LOWDR PGND DELAY
functional block diagram (TPS2848, TPS2849)
VCC Vr1
POR
SYS_UVLO
0.9 × Vref
PWRRDY AGND
THERMAL SHUTDOWN
SHUTDOWN
DRIVE REGULATOR
VDRV
VCC
REFERENCES
Vref Vr1 0.9 × Vref SHUTDOWN
BOOT
IN
DT ENABLE
INVERTING OPTION TPS2849 ONLY
VDRV
SYS_UVLO DEADTIME CONTROL
HIGHDR BOOTLO
LOWDR PGND DELAY
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TPS2838, TPS2839 TPS2848, TPS2849 ą
SLVS367A − MARCH 2001 − REVISED JUNE 2001
Terminal Functions
NAME
TERMINAL NO.
TPS283x TPS284x
DESCRIPTION
ADJ 6 .