Timer. TLC555-Q1 Datasheet

TLC555-Q1 Datasheet PDF


Part

TLC555-Q1

Description

Timer

Manufacture

etcTI

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Datasheet
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TLC555-Q1 Datasheet
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TLC555-Q1
SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015
TLC555-Q1 LinCMOS™ TIMER
1 Features
1 Qualified for Automotive Applications
• Very Low Power Consumption
– 1 mW (Typical) at VDD = 5 V
• Capable of Operation in Astable Mode
• CMOS Output Capable of Swinging Rail to Rail
• High-Output-Current Capability
– Sink 100 mA (Typical)
– Source 10 mA (Typical)
• Output Fully Compatible With CMOS, TTL, and
MOS
• Low Supply Current Reduces Spikes During
Output Transitions
• Single-Supply Operation From 2 V to 15 V
• Functionally Interchangeable With the NE555;
Has Same Pinout
2 Applications
• Precision Timing
• Pulse Generation
• Sequential Timing
• Time Delay Generation
• Pulse Width Modulation
• Pulse Position Modulation
• Linear Ramp Generators
• Automotive Lamp/LED Lighting
• Telematics
Pulse Width Modulator
TRIG
GND
VCC
TRIG
DISCH
0.1 µF
VS
RA
3 Description
The TLC555-Q1 is a monolithic timing circuit
fabricated using the TI LinCMOS™ process. The
timer is fully compatible with CMOS, TTL, and MOS
logic and operates at frequencies up to 2 MHz.
Because of its high input impedance, this device uses
smaller timing capacitors than those used by the
NE555. As a result, more accurate time delays and
oscillations are possible. Power consumption is low
across the full range of power-supply voltage.
Like the NE555, the TLC555-Q1 has a trigger level
equal to approximately one-third of the supply voltage
and a threshold level equal to approximately two-
thirds of the supply voltage. These levels can be
altered by use of the control voltage terminal (CONT).
When the trigger input (TRIG) falling below the trigger
level sets the flip-flop, and the output goes high.
Having TRIG above the trigger level and the
threshold input (THRES) above the threshold level
resets the flip-flop, and the output is low. The reset
input (RESET) can override all other inputs, and a
possible use is to initiate a new timing cycle. RESET
going low resets the flip-flop, and the output is low.
Whenever the output is low, a low-impedance path
exists between the discharge terminal (DISCH) and
GND. Tie all unused inputs to an appropriate logic
level to prevent false triggering.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLC555-Q1
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Pulse Width Modulator Waveform:
Top Waveform - Modulation
Bottom Waveform - Output Voltage
OUT
tH
RESET
(VS)
OUT
THRES
TLC555-Q1
RESET CONT
C
Modulation Input
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLC555-Q1 Datasheet
TLC555-Q1
SLFS078B – OCTOBER 2006 – REVISED OCTOBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics: VDD = 5 V......................... 5
7.6 Electrical Characteristics: VDD = 15 V....................... 6
7.7 Operating Characteristics.......................................... 6
7.8 Dissipation Ratings ................................................... 7
7.9 Typical Characteristics .............................................. 7
8 Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 8
8.4 Device Functional Modes........................................ 11
9 Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Applications ................................................ 13
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Community Resource............................................ 20
12.2 Trademarks ........................................................... 20
12.3 Electrostatic Discharge Caution ............................ 20
12.4 Glossary ................................................................ 20
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2012) to Revision B
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Original (October 2006) to Revision A
Page
• Changed next-to-last paragraph in Description and Ordering Information section ................................................................ 1
• In the 5-V and 15-V Electrical Characteristics tables, changed all "MAX" entries in the TA column to "Full range" ............. 5
• Deleted the last Electrical Characteristics table, which contained only redundant data ........................................................ 6
2 Submit Documentation Feedback
Product Folder Links: TLC555-Q1
Copyright © 2006–2015, Texas Instruments Incorporated


Features Datasheet pdf Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TLC555-Q1 SLFS078B – OCTOB ER 2006 – REVISED OCTOBER 2015 TLC555 -Q1 LinCMOS™ TIMER 1 Features •1 Q ualified for Automotive Applications Very Low Power Consumption – 1 mW ( Typical) at VDD = 5 V • Capable of Op eration in Astable Mode • CMOS Output Capable of Swinging Rail to Rail • H igh-Output-Current Capability – Sink 100 mA (Typical) – Source 10 mA (Typi cal) • Output Fully Compatible With C MOS, TTL, and MOS • Low Supply Curren t Reduces Spikes During Output Transiti ons • Single-Supply Operation From 2 V to 15 V • Functionally Interchangea ble With the NE555; Has Same Pinout 2 A pplications • Precision Timing • Pu lse Generation • Sequential Timing Time Delay Generation • Pulse Width Modulation • Pulse Position Modulati on • Linear Ramp Generators • Autom otive Lamp/LED Lighting • Telematics Pulse Width Modulator TRIG GND VCC TRIG DISCH 0.1 µF VS RA 3 Description The TLC555-Q1 is a monolithic .
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